image/svg+xml UMONITOR—User Level Set Up Monitor Address Instruction Operand Encoding 1 Description The UMONITOR instruction arms address monitoring hardware using an address specified in the source register (the address range that the monitoring hardware checks for store operations can be determined by using the CPUID monitor leaf function, EAX=05H). A store to an address within the specified address range triggers the monitoring hardware. The state of monitor hardware is used by UMWAIT. The content of the source register is an effective address. By default, the DS segment is used to create a linear address that is monitored. Segment overrides can be used. The address range must use memory of the write-back type. Only write-back memory is guaranteed to correctly trigger the monitoring hardware. Additional information on determining what address range to use in order to prevent false wake-ups is described in Chapter 8, “Multiple- Processor Management” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A . The UMONITOR instruction is ordered as a load operation with respect to other memory transactions. The instruc- tion is subject to the permission checking and faults associated with a byte load. Like a load, UMONITOR sets the A-bit but not the D-bit in page tables. UMONITOR and UMWAIT are available when CPUID.7.0:ECX.WAITPKG[bit 5] is enumerated as 1. UMONITOR and UMWAIT may be executed at any privilege level. Except for the width of the source register, the instruction’s oper- ation is the same in non-64-bit modes and in 64-bit mode. UMONITOR does not interoperate with the legacy MWAIT instruction. If UMONITOR was executed prior to executing MWAIT and following the most recent execution of the legacy MONITOR instruction, MWAIT will not enter an opti- mized state. Execution will continue to the instruction following MWAIT. The UMONITOR instruction causes a transactional abort when used inside a transactional region. The width of the source register (16b, 32b or 64b) is determined by the effective addressing width, which is affected in the standard way by the machine mode settings and 67 prefix. Operation UMONITOR sets up an address range for the monitor hardware using the content of source register as an effective address and puts the monitor hardware in armed state. A store to the specified address range will trigger the monitor hardware. Intel C/C ++ Compiler Intrinsic Equivalent UMONITOR void _umonitor(void *address); Numeric Exceptions None Opcode / Instruction Op/ En 64/32 bit Mode Support CPUID Feature Flag Description F3 0F AE /6 UMONITOR r16/r32/r64 AV/VWAITPKGSets up a linear address range to be monitored by hardware and activates the monitor. The address range should be a write-back memory caching type. The address is contained in r16/r32/r64. Op/EnTupleOperand 1Operand 2Operand 3Operand 4 ANAModRM:r/m (r)NANANA 1.The Mod field of the ModR/M byte must have value 11B. image/svg+xml Protected Mode Exceptions #GP(0) If the specified segment is not SS and the source register is outside the specified segment limit. If the specified segment register contains a NULL segment selector. #SS(0) If the specified segment is SS and the source register is outside the SS segment limit. #PF(fault-code) For a page fault. #UD If CPUID.7.0:ECX.WAITPKG[bit 5]=0. Real Address Mode Exceptions #GP If the specified segment is not SS and the source register is outside of the effective address space from 0 to FFFFH. #SS If the specified segment is SS and the source register is outside of the effective address space from 0 to FFFFH. #UD If CPUID.7.0:ECX.WAITPKG[bit 5]=0. Virtual 8086 Mode Exceptions Same exceptions as in real address mode; additionally: #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in protected mode. 64-Bit Mode Exceptions #GP(0)If the specified segment is not SS and the linear address is in non-canonical form. #SS(0)If the specified segment is SS and the source register is in non-canonical form. #PF(fault-code) For a page fault. #UDIf CPUID.7.0:ECX.WAITPKG[bit 5]=0. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .