image/svg+xmlUD—Undefined InstructionInstruction Operand EncodingDescriptionGenerates an invalid opcode exception. This instruction is provided for software testing to explicitly generate an invalid opcode exception. The opcodes for this instruction are reserved for this purpose.Other than raising the invalid opcode exception, this instruction has no effect on processor state or memory.Even though it is the execution of the UD instruction that causes the invalid opcode exception, the instruction pointer saved by delivery of the exception references the UD instruction (and not the following instruction).This instruction’s operation is the same in non-64-bit modes and 64-bit mode.Operation#UD (* Generates invalid opcode exception *);Flags AffectedNone.Exceptions (All Operating Modes)#UDRaises an invalid opcode exception in all operating modes.OpcodeInstructionOp/ En64-Bit ModeCompat/Leg ModeDescription0F FF /rUD01 r32, r/m32NOTES:1. Some processors decode the UD0 instruction without a ModR/M byte. As a result, those processors would deliver an invalid-opcode exception instead of a fault on instruction fetch when the instruction with a ModR/M byte (and any implied bytes) would cross a page or segment boundary.RMValidValidRaise invalid opcode exception.0F B9 /rUD1 r32, r/m32RMValidValidRaise invalid opcode exception.0F 0BUD2ZOValidValidRaise invalid opcode exception.Op/EnOperand 1Operand 2Operand 3Operand 4ZONANANANARMModRM:reg (r)ModRM:r/m (r)NANA

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.