image/svg+xmlUCOMISS—Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS Instruction Operand EncodingDescriptionCompares the single-precision floating-point values in the low doublewords of operand 1 (first operand) and operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unor-dered, greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unor-dered result is returned if either source operand is a NaN (QNaN or SNaN).Operand 1 is an XMM register; operand 2 can be an XMM register or a 32 bit memory location. The UCOMISS instruction differs from the COMISS instruction in that it signals a SIMD floating-point invalid opera-tion exception (#I) only if a source operand is an SNaN. The COMISS instruction signals an invalid operation excep-tion when a source operand is either a QNaN or SNaN.The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.Software should ensure VCOMISS is encoded with VEX.L=0. Encoding VCOMISS with VEX.L=1 may encounter unpredictable behavior across different processor generations.Operation(V)UCOMISS (all versions)RESULT := UnorderedCompare(DEST[31:0] <> SRC[31:0]) {(* Set EFLAGS *) CASE (RESULT) OFUNORDERED: ZF,PF,CF := 111;GREATER_THAN: ZF,PF,CF := 000;LESS_THAN: ZF,PF,CF := 001;EQUAL: ZF,PF,CF := 100;ESAC;OF, AF, SF := 0; }Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F 2E /rUCOMISS xmm1, xmm2/m32AV/VSSECompare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly.VEX.LIG.0F.WIG 2E /rVUCOMISS xmm1, xmm2/m32AV/VAVXCompare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly.EVEX.LLIG.0F.W0 2E /rVUCOMISS xmm1, xmm2/m32{sae}BV/VAVX512FCompare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r)ModRM:r/m (r)NANABTuple1 ScalarModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentVUCOMISSint _mm_comi_round_ss(__m128 a, __m128 b, int imm, int sae); UCOMISSint _mm_ucomieq_ss(__m128 a, __m128 b);UCOMISS int _mm_ucomilt_ss(__m128 a, __m128 b);UCOMISS int _mm_ucomile_ss(__m128 a, __m128 b);UCOMISS int _mm_ucomigt_ss(__m128 a, __m128 b);UCOMISS int _mm_ucomige_ss(__m128 a, __m128 b);UCOMISSint _mm_ucomineq_ss(__m128 a, __m128 b);SIMD Floating-Point ExceptionsInvalid (if SNaN Operands), DenormalOther ExceptionsVEX-encoded instructions, see Table2-20, “Type 3 Class Exception Conditions”; additionally:#UDIf VEX.vvvv != 1111B.EVEX-encoded instructions, see Table2-48, “Type E3NF Class Exception Conditions”.

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