image/svg+xmlUCOMISD—Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS Instruction Operand EncodingDescriptionPerforms an unordered compare of the double-precision floating-point values in the low quadwords of operand 1 (first operand) and operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered, greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result is returned if either source operand is a NaN (QNaN or SNaN).Operand 1 is an XMM register; operand 2 can be an XMM register or a 64 bit memorylocation. The UCOMISD instruction differs from the COMISD instruction in that it signals a SIMD floating-point invalid oper-ation exception (#I) only when a source operand is an SNaN. The COMISD instruction signals an invalid operation exception only if a source operand is either an SNaN or a QNaN.The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.Software should ensure VCOMISD is encoded with VEX.L=0. Encoding VCOMISD with VEX.L=1 may encounter unpredictable behavior across different processor generations.Operation(V)UCOMISD (all versions)RESULT := UnorderedCompare(DEST[63:0] <> SRC[63:0]) {(* Set EFLAGS *) CASE (RESULT) OFUNORDERED: ZF,PF,CF := 111;GREATER_THAN: ZF,PF,CF := 000;LESS_THAN: ZF,PF,CF := 001;EQUAL: ZF,PF,CF := 100;ESAC;OF, AF, SF := 0; }Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F 2E /rUCOMISD xmm1, xmm2/m64AV/VSSE2Compare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly.VEX.LIG.66.0F.WIG 2E /rVUCOMISD xmm1, xmm2/m64AV/VAVXCompare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly.EVEX.LLIG.66.0F.W1 2E /rVUCOMISD xmm1, xmm2/m64{sae}BV/VAVX512FCompare low double-precision floating-point values in xmm1 and xmm2/m64 and set the EFLAGS flags accordingly.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r)ModRM:r/m (r)NANABTuple1 ScalarModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentVUCOMISD int _mm_comi_round_sd(__m128d a, __m128d b, int imm, int sae); UCOMISD int _mm_ucomieq_sd(__m128d a, __m128d b)UCOMISD int _mm_ucomilt_sd(__m128d a, __m128d b)UCOMISD int _mm_ucomile_sd(__m128d a, __m128d b)UCOMISD int _mm_ucomigt_sd(__m128d a, __m128d b)UCOMISD int _mm_ucomige_sd(__m128d a, __m128d b)UCOMISD int _mm_ucomineq_sd(__m128d a, __m128d b)SIMD Floating-Point ExceptionsInvalid (if SNaN operands), DenormalOther ExceptionsVEX-encoded instructions, see Table2-20, “Type 3 Class Exception Conditions”; additionally:#UDIf VEX.vvvv != 1111B.EVEX-encoded instructions, see Table2-48, “Type E3NF Class Exception Conditions”.

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