image/svg+xmlSUBSS—Subtract Scalar Single-Precision Floating-Point ValueInstruction Operand EncodingDescriptionSubtract the low single-precision floating-point value from the second source operand and the first source operand and store the double-precision floating-point result in the low doubleword of the destination operand.The second source operand can be an XMM register or a 32-bit memory location. The first source and destination operands are XMM registers. 128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAXVL-1:32) of the corresponding destination register remain unchanged.VEX.128 and EVEX encoded versions: Bits (127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.EVEX encoded version: The low doubleword element of the destination operand is updated according to the writemask.Software should ensure VSUBSS is encoded with VEX.L=0. Encoding VSUBSD with VEX.L=1 may encounter unpre-dictable behavior across different processor generations.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionF3 0F 5C /rSUBSS xmm1, xmm2/m32AV/VSSESubtract the low single-precision floating-point value in xmm2/m32 from xmm1 and store the result in xmm1.VEX.LIG.F3.0F.WIG 5C /rVSUBSS xmm1,xmm2, xmm3/m32BV/VAVXSubtract the low single-precision floating-point value in xmm3/m32 from xmm2 and store the result in xmm1.EVEX.LLIG.F3.0F.W0 5C /rVSUBSS xmm1 {k1}{z}, xmm2, xmm3/m32{er}CV/VAVX512FSubtract the low single-precision floating-point value in xmm3/m32 from xmm2 and store the result in xmm1 under writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACTuple1 ScalarModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlOperationVSUBSS (EVEX encoded version)IF (SRC2 *is register*) AND (EVEX.b = 1) THENSET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);FI;IF k1[0] or *no writemask*THENDEST[31:0] := SRC1[31:0] - SRC2[31:0]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[31:0] remains unchanged*ELSE ; zeroing-maskingTHEN DEST[31:0] := 0FI;FI;DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0VSUBSS (VEX.128 encoded version)DEST[31:0] := SRC1[31:0] - SRC2[31:0]DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0SUBSS (128-bit Legacy SSE version)DEST[31:0] := DEST[31:0] - SRC[31:0]DEST[MAXVL-1:32] (Unmodified)Intel C/C++ Compiler Intrinsic EquivalentVSUBSS __m128 _mm_mask_sub_ss (__m128 s, __mmask8 k, __m128 a, __m128 b);VSUBSS __m128 _mm_maskz_sub_ss (__mmask8 k, __m128 a, __m128 b);VSUBSS __m128 _mm_sub_round_ss (__m128 a, __m128 b, int);VSUBSS __m128 _mm_mask_sub_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int);VSUBSS __m128 _mm_maskz_sub_round_ss (__mmask8 k, __m128 a, __m128 b, int);SUBSS __m128 _mm_sub_ss (__m128 a, __m128 b);SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, DenormalOther ExceptionsVEX-encoded instructions, see Table2-20, “Type 3 Class Exception Conditions”.EVEX-encoded instructions, see Table2-47, “Type E3 Class Exception Conditions”.

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