SUBSS—Subtract Scalar Single-Precision Floating-Point ValueInstruction Operand EncodingDescriptionSubtract the low single-precision floating-point value from the second source operand and the first source operand and store the double-precision floating-point result in the low doubleword of the destination operand.The second source operand can be an XMM register or a 32-bit memory location. The first source and destination operands are XMM registers. 128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAXVL-1:32) of the corresponding destination register remain unchanged.VEX.128 and EVEX encoded versions: Bits (127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.EVEX encoded version: The low doubleword element of the destination operand is updated according to the writemask.Software should ensure VSUBSS is encoded with VEX.L=0. Encoding VSUBSD with VEX.L=1 may encounter unpre-dictable behavior across different processor generations.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionF3 0F 5C /rSUBSS xmm1, xmm2/m32AV/VSSESubtract the low single-precision floating-point value in xmm2/m32 from xmm1 and store the result in xmm1.VEX.LIG.F3.0F.WIG 5C /rVSUBSS xmm1,xmm2, xmm3/m32BV/VAVXSubtract the low single-precision floating-point value in xmm3/m32 from xmm2 and store the result in xmm1.EVEX.LLIG.F3.0F.W0 5C /rVSUBSS xmm1 {k1}{z}, xmm2, xmm3/m32{er}CV/VAVX512FSubtract the low single-precision floating-point value in xmm3/m32 from xmm2 and store the result in xmm1 under writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACTuple1 ScalarModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA
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