SUBPD—Subtract Packed Double-Precision Floating-Point ValuesInstruction Operand EncodingDescriptionPerforms a SIMD subtract of the two, four or eight packed double-precision floating-point values of the second Source operand from the first Source operand, and stores the packed double-precision floating-point results in the destination operand.VEX.128 and EVEX.128 encoded versions: The second source operand is an XMM register or an 128-bit memory location. The first source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the corre-sponding destination register are zeroed.VEX.256 and EVEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first source operand and destination operands are YMM registers. Bits (MAXVL-1:256) of the corre-sponding destination register are zeroed.EVEX.512 encoded version: The second source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit memory location. The first source operand and destination operands are ZMM registers. The destination operand is conditionally updated according to the writemask.128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper Bits (MAXVL-1:128) of the corresponding register destination are unmodified.Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F 5C /rSUBPD xmm1, xmm2/m128AV/VSSE2Subtract packed double-precision floating-point values in xmm2/mem from xmm1 and store result in xmm1.VEX.128.66.0F.WIG 5C /rVSUBPD xmm1,xmm2, xmm3/m128BV/VAVXSubtract packed double-precision floating-point values in xmm3/mem from xmm2 and store result in xmm1.VEX.256.66.0F.WIG 5C /rVSUBPD ymm1, ymm2, ymm3/m256BV/VAVXSubtract packed double-precision floating-point values in ymm3/mem from ymm2 and store result in ymm1.EVEX.128.66.0F.W1 5C /rVSUBPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst CV/VAVX512VLAVX512FSubtract packed double-precision floating-point values from xmm3/m128/m64bcst to xmm2 and store result in xmm1 with writemask k1.EVEX.256.66.0F.W1 5C /rVSUBPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstCV/VAVX512VLAVX512FSubtract packed double-precision floating-point values from ymm3/m256/m64bcst to ymm2 and store result in ymm1 with writemask k1.EVEX.512.66.0F.W1 5C /rVSUBPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}CV/VAVX512FSubtract packed double-precision floating-point values from zmm3/m512/m64bcst to zmm2 and store result in zmm1 with writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACFullModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA
This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.