image/svg+xml STMXCSR—Store MXCSR Register State Instruction Operand Encoding Description Stores the contents of the MXCSR control and status register to the destination operand. The destination operand is a 32-bit memory location. The reserved bits in the MXCSR register are stored as 0s. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. VEX.L must be 0, otherwise instructions will #UD. Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD. Operation m32 := MXCSR; Intel C/C ++ Compiler Intrinsic Equivalent _mm_getcsr(void) SIMD Floating-Point Exceptions None. Other Exceptions See Table2-22, “Type 5 Class Exception Conditions”; additionally: #UDIf VEX.L= 1, If VEX.vvvv ≠ 1111B. Opcode*/ Instruction Op/ En 64/32 bit Mode Support CPUID Feature Flag Description NP 0F AE /3 STMXCSR m32 MV/VSSEStore contents of MXCSR register to m32 . VEX.LZ.0F.WIG AE /3 VSTMXCSR m32 MV/VAVXStore contents of MXCSR register to m32 . Op/EnOperand 1Operand 2Operand 3Operand 4 MModRM:r/m (w)NANANA This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .