image/svg+xmlSQRTSS—Compute Square Root of Scalar Single-Precision Value Instruction Operand EncodingDescriptionComputes the square root of the low single-precision floating-point value in the second source operand and stores the single-precision floating-point result in the destination operand. The second source operand can be an XMM register or a 32-bit memory location. The first source and destination operands is an XMM register. 128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL-1:32) of the corresponding YMM destination register remain unchanged.VEX.128 and EVEX encoded versions: Bits 127:32 of the destination operand are copied from the corresponding bits of the first source operand. Bits (MAXVL-1:128) of the destination ZMM register are zeroed.EVEX encoded version: The low doubleword element of the destination operand is updated according to the writemask.Software should ensure VSQRTSS is encoded with VEX.L=0. Encoding VSQRTSS with VEX.L=1 may encounter unpredictable behavior across different processor generations.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionF3 0F 51 /rSQRTSS xmm1, xmm2/m32AV/VSSEComputes square root of the low single-precision floating-point value in xmm2/m32 and stores the results in xmm1.VEX.LIG.F3.0F.WIG 51 /rVSQRTSS xmm1, xmm2, xmm3/m32BV/VAVXComputes square root of the low single-precision floating-point value in xmm3/m32 and stores the results in xmm1. Also, upper single-precision floating-point values (bits[127:32]) from xmm2 are copied to xmm1[127:32].EVEX.LLIG.F3.0F.W0 51 /rVSQRTSS xmm1 {k1}{z}, xmm2, xmm3/m32{er}CV/VAVX512FComputes square root of the low single-precision floating-point value in xmm3/m32 and stores the results in xmm1 under writemask k1. Also, upper single-precision floating-point values (bits[127:32]) from xmm2 are copied to xmm1[127:32].Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACTuple1 ScalarModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlOperationVSQRTSS (EVEX encoded version)IF (EVEX.b = 1) AND (SRC2 *is register*)THENSET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);FI;IF k1[0] or *no writemask*THENDEST[31:0] := SQRT(SRC2[31:0])ELSE IF *merging-masking*; merging-maskingTHEN *DEST[31:0] remains unchanged*ELSE ; zeroing-maskingDEST[31:0] := 0FI;FI;DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0VSQRTSS (VEX.128 encoded version)DEST[31:0] := SQRT(SRC2[31:0])DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0SQRTSS (128-bit Legacy SSE version)DEST[31:0] := SQRT(SRC2[31:0])DEST[MAXVL-1:32] (Unmodified)Intel C/C++ Compiler Intrinsic EquivalentVSQRTSS __m128 _mm_sqrt_round_ss(__m128 a, __m128 b, int r);VSQRTSS __m128 _mm_mask_sqrt_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int r);VSQRTSS __m128 _mm_maskz_sqrt_round_ss( __mmask8 k, __m128 a, __m128 b, int r);SQRTSS __m128 _mm_sqrt_ss(__m128 a)SIMD Floating-Point ExceptionsInvalid, Precision, DenormalOther ExceptionsNon-EVEX-encoded instruction, see Table2-20, “Type 3 Class Exception Conditions”.EVEX-encoded instruction, see Table2-47, “Type E3 Class Exception Conditions”.

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