image/svg+xmlSQRTPD—Square Root of Double-Precision Floating-Point ValuesInstruction Operand EncodingDescriptionPerforms a SIMD computation of the square roots of the two, four or eight packed double-precision floating-point values in the source operand (the second operand) stores the packed double-precision floating-point results in the destination operand (the first operand). EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register updated according to the writemask.VEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding ZMM register destination are zeroed.VEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destina-tion operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destina-tion is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified.Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F 51 /rSQRTPD xmm1, xmm2/m128AV/VSSE2Computes Square Roots of the packed double-precision floating-point values in xmm2/m128 and stores the result in xmm1.VEX.128.66.0F.WIG 51 /rVSQRTPD xmm1, xmm2/m128AV/VAVXComputes Square Roots of the packed double-precision floating-point values in xmm2/m128 and stores the result in xmm1.VEX.256.66.0F.WIG 51 /rVSQRTPD ymm1, ymm2/m256AV/VAVXComputes Square Roots of the packed double-precision floating-point values in ymm2/m256 and stores the result in ymm1.EVEX.128.66.0F.W1 51 /rVSQRTPD xmm1 {k1}{z}, xmm2/m128/m64bcstBV/VAVX512VLAVX512FComputes Square Roots of the packed double-precision floating-point values in xmm2/m128/m64bcst and stores the result in xmm1 subject to writemask k1.EVEX.256.66.0F.W1 51 /rVSQRTPD ymm1 {k1}{z}, ymm2/m256/m64bcstBV/VAVX512VLAVX512FComputes Square Roots of the packed double-precision floating-point values in ymm2/m256/m64bcst and stores the result in ymm1 subject to writemask k1.EVEX.512.66.0F.W1 51 /rVSQRTPD zmm1 {k1}{z}, zmm2/m512/m64bcst{er}BV/VAVX512FComputes Square Roots of the packed double-precision floating-point values in zmm2/m512/m64bcst and stores the result in zmm1 subject to writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)NANABFullModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlOperationVSQRTPD (EVEX encoded versions)(KL, VL) = (2, 128), (4, 256), (8, 512)IF (VL = 512) AND (EVEX.b = 1) AND (SRC *is register*)THENSET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);FI;FOR j := 0 TO KL-1i := j * 64IF k1[j] OR *no writemask* THENIF (EVEX.b = 1) AND (SRC *is memory*)THEN DEST[i+63:i] := SQRT(SRC[63:0])ELSE DEST[i+63:i] := SQRT(SRC[i+63:i])FI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+63:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+63:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0VSQRTPD (VEX.256 encoded version)DEST[63:0] := SQRT(SRC[63:0])DEST[127:64] := SQRT(SRC[127:64])DEST[191:128] := SQRT(SRC[191:128])DEST[255:192] := SQRT(SRC[255:192])DEST[MAXVL-1:256] := 0.VSQRTPD (VEX.128 encoded version)DEST[63:0] := SQRT(SRC[63:0])DEST[127:64] := SQRT(SRC[127:64])DEST[MAXVL-1:128] := 0SQRTPD (128-bit Legacy SSE version)DEST[63:0] := SQRT(SRC[63:0])DEST[127:64] := SQRT(SRC[127:64])DEST[MAXVL-1:128] (Unmodified)Intel C/C++ Compiler Intrinsic EquivalentVSQRTPD __m512d _mm512_sqrt_round_pd(__m512d a, int r);VSQRTPD __m512d _mm512_mask_sqrt_round_pd(__m512d s, __mmask8 k, __m512d a, int r);VSQRTPD __m512d _mm512_maskz_sqrt_round_pd( __mmask8 k, __m512d a, int r);VSQRTPD __m256d _mm256_sqrt_pd (__m256d a);VSQRTPD __m256d _mm256_mask_sqrt_pd(__m256d s, __mmask8 k, __m256d a, int r);VSQRTPD __m256d _mm256_maskz_sqrt_pd( __mmask8 k, __m256d a, int r);SQRTPD __m128d _mm_sqrt_pd (__m128d a);VSQRTPD __m128d _mm_mask_sqrt_pd(__m128d s, __mmask8 k, __m128d a, int r);VSQRTPD __m128d _mm_maskz_sqrt_pd( __mmask8 k, __m128d a, int r);

image/svg+xmlSIMD Floating-Point ExceptionsInvalid, Precision, DenormalOther ExceptionsNon-EVEX-encoded instruction, see Table2-19, “Type 2 Class Exception Conditions”; additionally:#UDIf VEX.vvvv != 1111B.EVEX-encoded instruction, see Table2-46, “Type E2 Class Exception Conditions”; additionally:#UDIf EVEX.vvvv != 1111B.

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