image/svg+xmlSHRD—Double Precision Shift RightInstruction Operand EncodingDescriptionThe SHRD instruction is useful for multi-precision shifts of 64 bits or more.The instruction shifts the first operand (destination operand) to the right the number of bits specified by the third operand (count operand). The second operand (source operand) provides bits to shift in from the left (starting with the most significant bit of the destination operand). The destination operand can be a register or a memory location; the source operand is a register. The count operand is an unsigned integer that can be stored in an immediate byte or the CL register. If the count operand is CL, the shift count is the logical AND of CL and a count mask. In non-64-bit modes and default 64-bit mode, the width of the count mask is 5 bits. Only bits 0 through 4 of the count register are used (masking the count to a value between 0 and 31). If the count is greater than the operand size, the result is undefined.If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. If the count operand is 0, flags are not affected.In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits (upgrading the count mask to 6 bits). See the summary chart at the beginning of this section for encoding data and limits.OperationIF (In 64-Bit Mode and REX.W = 1) THEN COUNT := COUNT MOD 64;ELSE COUNT := COUNT MOD 32;FISIZE := OperandSize;IF COUNT = 0THEN No operation;ELSEOpcode*InstructionOp/ En64-Bit ModeCompat/Leg ModeDescription0F AC /r ibSHRD r/m16, r16, imm8MRIValid ValidShift r/m16 to right imm8 places while shifting bits from r16 in from the left.0F AD /rSHRD r/m16, r16, CLMRCValid ValidShift r/m16 to right CL places while shifting bits from r16 in from the left.0F AC /r ibSHRD r/m32, r32, imm8MRIValid ValidShift r/m32 to right imm8 places while shifting bits from r32 in from the left.REX.W + 0F AC /r ibSHRD r/m64, r64, imm8MRIValidN.E.Shift r/m64 to right imm8 places while shifting bits from r64 in from the left.0F AD /rSHRD r/m32, r32, CLMRCValid ValidShift r/m32 to right CL places while shifting bits from r32 in from the left.REX.W + 0F AD /rSHRD r/m64, r64, CLMRCValid N.E.Shift r/m64 to right CL places while shifting bits from r64 in from the left.Op/EnOperand 1Operand 2Operand 3Operand 4MRIModRM:r/m (w)ModRM:reg (r)imm8NAMRCModRM:r/m (w)ModRM:reg (r)CLNA

image/svg+xmlIF COUNT > SIZETHEN (* Bad parameters *)DEST is undefined;CF, OF, SF, ZF, AF, PF are undefined;ELSE (* Perform the shift *)CF := BIT[DEST, COUNT – 1]; (* Last bit shifted out on exit *)FOR i := 0 TO SIZE – 1 – COUNTDOBIT[DEST, i] := BIT[DEST, i + COUNT];OD;FOR i := SIZE – COUNT TO SIZE – 1DOBIT[DEST,i] := BIT[SRC, i + COUNT – SIZE];OD;FI;FI;Flags AffectedIf the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand and the SF, ZF, and PF flags are set according to the value of the result. For a 1-bit shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. For shifts greater than 1 bit, the OF flag is undefined. If a shift occurs, the AF flag is unde-fined. If the count operand is 0, the flags are not affected. If the count is greater than the operand size, the flags are undefined.Protected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made.#UD If the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.

image/svg+xml64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.