image/svg+xmlSHA256RNDS2—Perform Two Rounds of SHA256 OperationInstruction Operand EncodingDescriptionThe SHA256RNDS2 instruction performs 2 rounds of SHA256 operation using an initial SHA256 state (C,D,G,H) from the first operand, an initial SHA256 state (A,B,E,F) from the second operand, and a pre-computed sum of the next 2 round message dwords and the corresponding round constants from the implicit operand xmm0. Note that only the two lower dwords of XMM0 are used by the instruction.The updated SHA256 state (A,B,E,F) is written to the first operand, and the second operand can be used as the updated state (C,D,G,H) in later rounds.OperationSHA256RNDS2 A_0 := SRC2[127:96]; B_0 := SRC2[95:64]; C_0 := SRC1[127:96]; D_0 := SRC1[95:64]; E_0 := SRC2[63:32]; F_0 := SRC2[31:0]; G_0 := SRC1[63:32]; H_0 := SRC1[31:0]; WK0 := XMM0[31: 0]; WK1 := XMM0[63: 32]; FOR i = 0 to 1A_(i +1) := Ch (E_i, F_i, G_i) +Σ1( E_i) +WKi+ H_i + Maj(A_i , B_i, C_i) +Σ0( A_i); B_(i +1) := A_i; C_(i +1) := B_i ; D_(i +1) := C_i; E_(i +1) := Ch (E_i, F_i, G_i) +Σ1( E_i) +WKi+ H_i + D_i; F_(i +1) := E_i ; G_(i +1) := F_i; H_(i +1) := G_i; ENDFORDEST[127:96] := A_2; DEST[95:64] := B_2; DEST[63:32] := E_2; DEST[31:0] := F_2; Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F 38 CB /r SHA256RNDS2 xmm1, xmm2/m128, <XMM0>RMIV/VSHAPerform 2 rounds of SHA256 operation using an initial SHA256 state (C,D,G,H) from xmm1, an initial SHA256 state (A,B,E,F) from xmm2/m128, and a pre-computed sum of the next 2 round mes-sage dwords and the corresponding round constants from the implicit operand XMM0, storing the updated SHA256 state (A,B,E,F) result in xmm1.Op/EnOperand 1Operand 2Operand 3RMIModRM:reg (r, w)ModRM:r/m (r)Implicit XMM0 (r)

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentSHA256RNDS2: __m128i _mm_sha256rnds2_epu32(__m128i, __m128i, __m128i);Flags AffectedNoneSIMD Floating-Point ExceptionsNoneOther ExceptionsSee Table2-21, “Type 4 Class Exception Conditions”.

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