image/svg+xmlSETcc—Set Byte on ConditionOpcodeInstructionOp/ En64-Bit ModeCompat/Leg ModeDescription0F 97SETA r/m8MValid ValidSet byte if above (CF=0 and ZF=0).REX + 0F 97SETA r/m8*MValidN.E.Set byte if above (CF=0 and ZF=0).0F 93SETAE r/m8MValid ValidSet byte if above or equal (CF=0).REX + 0F 93SETAE r/m8*MValidN.E.Set byte if above or equal (CF=0).0F 92SETB r/m8MValid ValidSet byte if below (CF=1).REX + 0F 92SETB r/m8*MValidN.E.Set byte if below (CF=1).0F 96SETBE r/m8MValid ValidSet byte if below or equal (CF=1 or ZF=1).REX + 0F 96SETBE r/m8*MValidN.E.Set byte if below or equal (CF=1 or ZF=1).0F 92SETC r/m8MValid ValidSet byte if carry (CF=1).REX + 0F 92SETC r/m8*MValidN.E.Set byte if carry (CF=1).0F 94SETE r/m8MValid ValidSet byte if equal (ZF=1).REX + 0F 94SETE r/m8*MValidN.E.Set byte if equal (ZF=1).0F 9FSETG r/m8MValid ValidSet byte if greater (ZF=0 and SF=OF).REX + 0F 9FSETG r/m8*MValidN.E.Set byte if greater (ZF=0 and SF=OF).0F 9DSETGE r/m8MValid ValidSet byte if greater or equal (SF=OF).REX + 0F 9DSETGE r/m8*MValidN.E.Set byte if greater or equal (SF=OF).0F 9CSETL r/m8MValid ValidSet byte if less (SF≠ OF).REX + 0F 9CSETL r/m8*MValidN.E.Set byte if less (SF≠ OF).0F 9ESETLE r/m8MValid ValidSet byte if less or equal (ZF=1 or SF≠ OF).REX + 0F 9ESETLE r/m8*MValidN.E.Set byte if less or equal (ZF=1 or SF≠ OF).0F 96SETNA r/m8MValid ValidSet byte if not above (CF=1 or ZF=1).REX + 0F 96SETNA r/m8*MValidN.E.Set byte if not above (CF=1 or ZF=1).0F 92SETNAE r/m8MValid ValidSet byte if not above or equal (CF=1).REX + 0F 92SETNAE r/m8*MValidN.E.Set byte if not above or equal (CF=1).0F 93SETNB r/m8MValid ValidSet byte if not below (CF=0).REX + 0F 93SETNB r/m8*MValidN.E.Set byte if not below (CF=0).0F 97SETNBE r/m8MValid ValidSet byte if not below or equal (CF=0 and ZF=0).REX + 0F 97SETNBE r/m8*MValidN.E.Set byte if not below or equal (CF=0 and ZF=0).0F 93SETNC r/m8MValid ValidSet byte if not carry (CF=0).REX + 0F 93SETNC r/m8*MValidN.E.Set byte if not carry (CF=0).0F 95SETNE r/m8MValid ValidSet byte if not equal (ZF=0).REX + 0F 95SETNE r/m8*MValidN.E.Set byte if not equal (ZF=0).0F 9ESETNG r/m8MValid ValidSet byte if not greater (ZF=1 or SF≠ OF)REX + 0F 9ESETNG r/m8*MValidN.E.Set byte if not greater (ZF=1 or SF≠ OF).0F 9CSETNGE r/m8MValid ValidSet byte if not greater or equal (SF≠ OF).REX + 0F 9CSETNGE r/m8*MValidN.E.Set byte if not greater or equal (SF≠ OF).0F 9DSETNL r/m8MValid ValidSet byte if not less (SF=OF).REX + 0F 9DSETNL r/m8*MValidN.E.Set byte if not less (SF=OF).0F 9FSETNLE r/m8MValid ValidSet byte if not less or equal (ZF=0 and SF=OF).

image/svg+xmlInstruction Operand EncodingDescriptionSets the destination operand to 0 or 1 depending on the settings of the status flags (CF, SF, OF, ZF, and PF) in the EFLAGS register. The destination operand points to a byte register or a byte in memory. The condition code suffix (cc) indicates the condition being tested for. The terms “above” and “below” are associated with the CF flag and refer to the relationship between two unsigned integer values. The terms “greater” and “less” are associated with the SF and OF flags and refer to the relationship between two signed integer values.Many of the SETcc instruction opcodes have alternate mnemonics. For example, SETG (set byte if greater) and SETNLE (set if not less or equal) have the same opcode and test for the same condition: ZF equals 0 and SF equals OF. These alternate mnemonics are provided to make code more intelligible. Appendix B, “EFLAGS Condition Codes,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, shows the alternate mnemonics for various test conditions.Some languages represent a logical one as an integer with all bits set. This representation can be obtained by choosing the logically opposite condition for the SETcc instruction, then decrementing the result. For example, to test for overflow, use the SETNO instruction, then decrement the result.REX + 0F 9FSETNLE r/m8*MValidN.E.Set byte if not less or equal (ZF=0 and SF=OF).0F 91SETNO r/m8MValid ValidSet byte if not overflow (OF=0).REX + 0F 91SETNO r/m8*MValidN.E.Set byte if not overflow (OF=0).0F 9BSETNP r/m8MValidValidSet byte if not parity (PF=0).REX + 0F 9BSETNP r/m8*MValidN.E.Set byte if not parity (PF=0).0F 99SETNS r/m8MValid ValidSet byte if not sign (SF=0).REX + 0F 99SETNS r/m8*MValidN.E.Set byte if not sign (SF=0).0F 95SETNZ r/m8MValid ValidSet byte if not zero (ZF=0).REX + 0F 95SETNZ r/m8*MValidN.E.Set byte if not zero (ZF=0).0F 90SETO r/m8MValid ValidSet byte if overflow (OF=1)REX + 0F 90SETO r/m8*MValidN.E.Set byte if overflow (OF=1).0F 9ASETP r/m8MValid ValidSet byte if parity (PF=1).REX + 0F 9ASETP r/m8*MValidN.E.Set byte if parity (PF=1).0F 9ASETPE r/m8MValid ValidSet byte if parity even (PF=1).REX + 0F 9ASETPE r/m8*MValidN.E.Set byte if parity even (PF=1).0F 9BSETPO r/m8MValid ValidSet byte if parity odd (PF=0).REX + 0F 9BSETPO r/m8*MValidN.E.Set byte if parity odd (PF=0).0F 98SETS r/m8MValid ValidSet byte if sign (SF=1).REX + 0F 98SETS r/m8*MValidN.E.Set byte if sign (SF=1).0F 94SETZ r/m8MValid ValidSet byte if zero (ZF=1).REX + 0F 94SETZ r/m8*MValid N.E.Set byte if zero (ZF=1).NOTES:*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. Op/EnOperand 1Operand 2Operand 3Operand 4MModRM:r/m (r)NANANAOpcodeInstructionOp/ En64-Bit ModeCompat/Leg ModeDescription

image/svg+xmlThe reg field of the ModR/M byte is not used for the SETCC instruction and those opcode bits are ignored by the processor.In IA-64 mode, the operand size is fixed at 8 bits. Use of REX prefix enable uniform addressing to additional byte registers. Otherwise, this instruction’s operation is the same as in legacy mode and compatibility mode. OperationIF conditionTHEN DEST := 1; ELSE DEST := 0; FI;Flags AffectedNone.Protected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#UD If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#UD If the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#UD If the LOCK prefix is used.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.