image/svg+xmlSAL/SAR/SHL/SHR—ShiftOpcode***InstructionOp/ En64-Bit ModeCompat/Leg ModeDescriptionD0 /4SAL r/m8, 1M1Valid ValidMultiply r/m8 by 2, once. REX + D0 /4SAL r/m8**, 1M1ValidN.E.Multiply r/m8 by 2, once. D2 /4SAL r/m8, CLMCValid ValidMultiply r/m8 by 2, CL times.REX + D2 /4SAL r/m8**, CLMCValidN.E.Multiply r/m8 by 2, CL times.C0 /4 ibSAL r/m8, imm8MIValid ValidMultiply r/m8 by 2, imm8 times.REX + C0 /4 ibSAL r/m8**, imm8MIValidN.E.Multiply r/m8 by 2, imm8 times.D1 /4SAL r/m16, 1M1Valid ValidMultiply r/m16 by 2, once.D3 /4SAL r/m16, CLMCValid ValidMultiply r/m16 by 2, CL times.C1 /4 ibSAL r/m16, imm8MIValid ValidMultiply r/m16 by 2, imm8 times.D1 /4SAL r/m32, 1M1Valid ValidMultiply r/m32 by 2, once.REX.W + D1 /4SAL r/m64, 1M1ValidN.E.Multiply r/m64 by 2, once.D3 /4SAL r/m32, CLMCValid ValidMultiply r/m32 by 2, CL times.REX.W + D3 /4SAL r/m64, CLMCValidN.E.Multiply r/m64 by 2, CL times.C1 /4 ibSAL r/m32, imm8MIValid ValidMultiply r/m32 by 2, imm8 times.REX.W + C1 /4 ibSAL r/m64, imm8MIValidN.E.Multiply r/m64 by 2, imm8 times.D0 /7SAR r/m8, 1M1Valid ValidSigned divide* r/m8 by 2, once.REX + D0 /7SAR r/m8**, 1M1ValidN.E.Signed divide* r/m8 by 2, once.D2 /7SAR r/m8, CLMCValid ValidSigned divide* r/m8 by 2, CL times.REX + D2 /7SAR r/m8**, CLMCValidN.E.Signed divide* r/m8 by 2, CL times.C0 /7 ibSAR r/m8, imm8MIValid ValidSigned divide* r/m8 by 2, imm8 times.REX + C0 /7 ibSAR r/m8**, imm8MIValidN.E.Signed divide* r/m8 by 2, imm8 times.D1 /7SAR r/m16,1M1Valid ValidSigned divide* r/m16 by 2, once.D3 /7SAR r/m16, CLMCValid ValidSigned divide* r/m16 by 2, CL times.C1 /7 ibSAR r/m16, imm8MIValid ValidSigned divide* r/m16 by 2, imm8 times.D1 /7SAR r/m32, 1M1Valid ValidSigned divide* r/m32 by 2, once.REX.W + D1 /7SAR r/m64, 1M1ValidN.E.Signed divide* r/m64 by 2, once.D3 /7SAR r/m32, CLMCValid ValidSigned divide* r/m32 by 2, CL times.REX.W + D3 /7SAR r/m64, CLMCValidN.E.Signed divide* r/m64 by 2, CL times.C1 /7 ibSAR r/m32, imm8MIValid ValidSigned divide* r/m32 by 2, imm8 times.REX.W + C1 /7 ibSAR r/m64, imm8MIValidN.E.Signed divide* r/m64 by 2, imm8 timesD0 /4SHL r/m8, 1M1Valid ValidMultiply r/m8 by 2, once.REX + D0 /4SHL r/m8**, 1M1ValidN.E.Multiply r/m8 by 2, once.D2 /4SHL r/m8, CLMCValid ValidMultiply r/m8 by 2, CL times.REX + D2 /4SHL r/m8**, CLMCValidN.E.Multiply r/m8 by 2, CL times.C0 /4 ibSHL r/m8, imm8MIValid ValidMultiply r/m8 by 2, imm8 times.REX + C0 /4 ibSHL r/m8**, imm8MIValidN.E.Multiply r/m8 by 2, imm8 times.D1 /4SHL r/m16,1M1Valid ValidMultiply r/m16 by 2, once.D3 /4SHL r/m16, CLMCValid ValidMultiply r/m16 by 2, CL times.C1 /4 ibSHL r/m16, imm8MIValid ValidMultiply r/m16 by 2, imm8 times.D1 /4SHL r/m32,1M1Valid ValidMultiply r/m32 by 2, once.

image/svg+xmlInstruction Operand EncodingDescriptionShifts the bits in the first operand (destination operand) to the left or right by the number of bits specified in the second operand (count operand). Bits shifted beyond the destination operand boundary are first shifted into the CF flag, then discarded. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand. The destination operand can be a register or a memory location. The count operand can be an immediate value or the CL register. The count is masked to 5 bits (or 6 bits if in 64-bit mode and REX.W is used). The count range is limited to 0 to 31 (or 63 if 64-bit mode and REX.W is used). A special opcode encoding is provided for a count of 1.The shift arithmetic left (SAL) and shift logical left (SHL) instructions perform the same operation; they shift the bits in the destination operand to the left (toward more significant bit locations). For each shift count, the most significant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared (see Figure 7-7 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1).OpcodeInstructionOp/ En64-Bit ModeCompat/Leg ModeDescriptionREX.W + D1 /4SHL r/m64,1M1ValidN.E.Multiply r/m64 by 2, once.D3 /4SHL r/m32, CLMCValid ValidMultiply r/m32 by 2, CL times.REX.W + D3 /4SHL r/m64, CLMCValidN.E.Multiply r/m64 by 2, CL times.C1 /4 ibSHL r/m32, imm8MIValid ValidMultiply r/m32 by 2, imm8 times.REX.W + C1 /4 ibSHL r/m64, imm8MIValidN.E.Multiply r/m64 by 2, imm8 times.D0 /5SHR r/m8,1M1Valid ValidUnsigned divide r/m8 by 2, once.REX + D0 /5SHR r/m8**, 1M1ValidN.E.Unsigned divide r/m8 by 2, once.D2 /5SHR r/m8, CLMCValid ValidUnsigned divide r/m8 by 2, CL times.REX + D2 /5SHR r/m8**, CLMCValidN.E.Unsigned divide r/m8 by 2, CL times.C0 /5 ibSHR r/m8, imm8MIValid ValidUnsigned divide r/m8 by 2, imm8 times.REX + C0 /5 ibSHR r/m8**, imm8MIValidN.E.Unsigned divide r/m8 by 2, imm8 times.D1 /5SHR r/m16, 1M1Valid ValidUnsigned divide r/m16 by 2, once.D3 /5SHR r/m16, CLMCValid ValidUnsigned divide r/m16 by 2, CL timesC1 /5 ibSHR r/m16, imm8MIValid ValidUnsigned divide r/m16 by 2, imm8 times.D1 /5SHR r/m32, 1M1Valid ValidUnsigned divide r/m32 by 2, once.REX.W + D1 /5SHR r/m64, 1M1ValidN.E.Unsigned divide r/m64 by 2, once.D3 /5SHR r/m32, CLMCValid ValidUnsigned divide r/m32 by 2, CL times.REX.W + D3 /5SHR r/m64, CLMCValidN.E.Unsigned divide r/m64 by 2, CL times.C1 /5 ibSHR r/m32, imm8MIValid ValidUnsigned divide r/m32 by 2, imm8 times.REX.W + C1 /5 ibSHR r/m64, imm8MIValid N.E.Unsigned divide r/m64 by 2, imm8 times.NOTES:*Not the same form of division as IDIV; rounding is toward negative infinity.** In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.***See IA-32 Architecture Compatibility section below.Op/EnOperand 1Operand 2Operand 3Operand 4M1ModRM:r/m (r, w)1NANAMCModRM:r/m (r, w)CLNANAMIModRM:r/m (r, w)imm8NANA

image/svg+xmlThe shift arithmetic right (SAR) and shift logical right (SHR) instructions shift the bits of the destination operand to the right (toward less significant bit locations). For each shift count, the least significant bit of the destination operand is shifted into the CF flag, and the most significant bit is either set or cleared depending on the instruction type. The SHR instruction clears the most significant bit (see Figure 7-8 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1); the SAR instruction sets or clears the most significant bit to correspond to the sign (most significant bit) of the original value in the destination operand. In effect, the SAR instruction fills the empty bit position’s shifted value with the sign of the unshifted value (see Figure 7-9 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1).The SAR and SHR instructions can be used to perform signed or unsigned division, respectively, of the destination operand by powers of 2. For example, using the SAR instruction to shift a signed integer 1 bit to the right divides the value by 2.Using the SAR instruction to perform a division operation does not produce the same result as the IDIV instruction. The quotient from the IDIV instruction is rounded toward zero, whereas the “quotient” of the SAR instruction is rounded toward negative infinity. This difference is apparent only for negative numbers. For example, when the IDIV instruction is used to divide -9 by 4, the result is -2 with a remainder of -1. If the SAR instruction is used to shift -9 right by two bits, the result is -3 and the “remainder” is +3; however, the SAR instruction stores only the most significant bit of the remainder (in the CF flag). The OF flag is affected only on 1-bit shifts. For left shifts, the OF flag is set to 0 if the most-significant bit of the result is the same as the CF flag (that is, the top two bits of the original operand were the same); otherwise, it is set to 1. For the SAR instruction, the OF flag is cleared for all 1-bit shifts. For the SHR instruction, the OF flag is set to the most-significant bit of the original operand.In 64-bit mode, the instruction’s default operation size is 32 bits and the mask width for CL is 5 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64-bits and sets the mask width for CL to 6 bits. See the summary chart at the beginning of this section for encoding data and limits.IA-32 Architecture CompatibilityThe 8086 does not mask the shift count. However, all other IA-32 processors (starting with the Intel 286 processor) do mask the shift count to 5 bits, resulting in a maximum count of 31. This masking is done in all operating modes (including the virtual-8086 mode) to reduce the maximum execution time of the instructions.OperationIF 64-Bit Mode and using REX.WTHENcountMASK := 3FH;ELSEcountMASK := 1FH;FItempCOUNT := (COUNT AND countMASK);tempDEST := DEST;WHILE (tempCOUNT ≠ 0)DOIF instruction is SAL or SHLTHEN CF := MSB(DEST);ELSE (* Instruction is SAR or SHR *)CF := LSB(DEST);FI;IF instruction is SAL or SHLTHEN DEST := DEST ∗ 2;ELSE IF instruction is SAR

image/svg+xmlTHEN DEST := DEST / 2; (* Signed divide, rounding toward negative infinity *)ELSE (* Instruction is SHR *)DEST := DEST / 2 ; (* Unsigned divide *)FI;FI;tempCOUNT := tempCOUNT – 1;OD;(* Determine overflow for the various instructions *)IF (COUNT and countMASK) = 1THENIF instruction is SAL or SHLTHEN OF := MSB(DEST) XOR CF;ELSE IF instruction is SARTHEN OF := 0;ELSE (* Instruction is SHR *)OF := MSB(tempDEST);FI;FI;ELSE IF (COUNT AND countMASK) = 0THENAll flags unchanged;ELSE (* COUNT not 1 or 0 *)OF := undefined;FI;FI;Flags AffectedThe CF flag contains the value of the last bit shifted out of the destination operand; it is undefined for SHL and SHR instructions where the count is greater than or equal to the size (in bits) of the destination operand. The OF flag is affected only for 1-bit shifts (see “Description” above); otherwise, it is undefined. The SF, ZF, and PF flags are set according to the result. If the count is 0, the flags are not affected. For a non-zero count, the AF flag is undefined.Protected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SS segment limit.#UDIf the LOCK prefix is used.

image/svg+xmlVirtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.