image/svg+xml SAHF—Store AH into Flags Instruction Operand Encoding Description Loads the SF, ZF, AF, PF, and CF flags of the EFLAGS register with values from the corresponding bits in the AH register (bits 7, 6, 4, 2, and 0, respectively). Bits 1, 3, and 5 of register AH are ignored; the corresponding reserved bits (1, 3, and 5) in the EFLAGS register remain as shown in the “Operation” section below. This instruction executes as described above in compatibility mode and legacy mode. It is valid in 64-bit mode only if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1. Operation IF IA-64 Mode THEN IF CPUID.80000001H.ECX[0] = 1; THEN RFLAGS(SF:ZF:0:AF:0:PF:1:CF) := AH; ELSE #UD; FI ELSE EFLAGS(SF:ZF:0:AF:0:PF:1:CF) := AH; FI; Flags Affected The SF, ZF, AF, PF, and CF flags are loaded with values from the AH register. Bits 1, 3, and 5 of the EFLAGS register are unaffected, with the values remaining 1, 0, and 0, respectively. Protected Mode Exceptions None. Real-Address Mode Exceptions None. Virtual-8086 Mode Exceptions None. Compatibility Mode Exceptions None. Opcode*InstructionOp/ En 64-Bit Mode Compat/ Leg Mode Description 9ESAHFZOInvalid*ValidLoads SF, ZF, AF, PF, and CF from AH into EFLAGS register. NOTES: * Valid in specific steppings. See Description section. Op/EnOperand 1Operand 2Operand 3Operand 4 ZONANANANA image/svg+xml 64-Bit Mode Exceptions #UD If CPUID.80000001H.ECX[0] = 0. If the LOCK prefix is used. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .