image/svg+xmlROUNDSD — Round Scalar Double Precision Floating-Point ValuesInstruction Operand EncodingDescriptionRound the DP FP value in the lower qword of the source operand (second operand) using the rounding mode spec-ified in the immediate operand (third operand) and place the result in the destination operand (first operand). The rounding process rounds a double-precision floating-point input to an integer value and returns the integer result as a double precision floating-point value in the lowest position. The upper double precision floating-point value in the destination is retained. The immediate operand specifies control fields for the rounding operation, three bit fields are defined and shown in Figure4-24. Bit 3 of the immediate byte controls processor behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (Table 4-23 lists the encoded values for rounding-mode field). The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before rounding.128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL-1:64) of the corresponding YMM destination register remain unchanged.VEX.128 encoded version: Bits (MAXVL-1:128) of the destination YMM register are zeroed.OperationIF (imm[2] = ‘1) THEN // rounding mode is determined by MXCSR.RC DEST[63:0] := ConvertDPFPToInteger_M(SRC[63:0]);ELSE// rounding mode is determined by IMM8.RCDEST[63:0] := ConvertDPFPToInteger_Imm(SRC[63:0]);FI;DEST[127:63] remains unchanged ;ROUNDSD (128-bit Legacy SSE version)DEST[63:0] := RoundToInteger(SRC[63:0], ROUND_CONTROL)DEST[MAXVL-1:64] (Unmodified)Opcode*/InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F 3A 0B /r ibROUNDSD xmm1, xmm2/m64, imm8RMIV/VSSE4_1Round the low packed double precision floating-point value in xmm2/m64 and place the result in xmm1. The rounding mode is determined by imm8.VEX.LIG.66.0F3A.WIG 0B /r ibVROUNDSD xmm1, xmm2, xmm3/m64, imm8RVMIV/VAVXRound the low packed double precision floating-point value in xmm3/m64 and place the result in xmm1. The rounding mode is determined by imm8. Upper packed double precision floating-point value (bits[127:64]) from xmm2 is copied to xmm1[127:64].Op/EnOperand 1Operand 2Operand 3Operand 4RMIModRM:reg (w)ModRM:r/m (r)imm8NARVMIModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)imm8

image/svg+xmlVROUNDSD (VEX.128 encoded version)DEST[63:0] := RoundToInteger(SRC2[63:0], ROUND_CONTROL)DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0Intel C/C++ Compiler Intrinsic EquivalentROUNDSD:__m128d mm_round_sd(__m128d dst, __m128d s1, int iRoundMode);__m128d mm_floor_sd(__m128d dst, __m128d s1);__m128d mm_ceil_sd(__m128d dst, __m128d s1);SIMD Floating-Point ExceptionsInvalid (signaled only if SRC = SNaN)Precision (signaled only if imm[3] = ‘0; if imm[3] = ‘1, then the Precision Mask in the MXSCSR is ignored and preci-sion exception is not signaled.)Note that Denormal is not signaled by ROUNDSD.Other ExceptionsSee Table2-20, “Type 3 Class Exception Conditions”.

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