image/svg+xml RORX — Rotate Right Logical Without Affecting Flags Instruction Operand Encoding Description Rotates the bits of second operand right by the count value specified in imm8 without affecting arithmetic flags. The RORX instruction does not read or write the arithmetic flags. This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD. Operation IF (OperandSize = 32) y := imm8 AND 1FH; DEST := (SRC >> y) | (SRC << (32-y)); ELSEIF (OperandSize = 64 ) y := imm8 AND 3FH; DEST := (SRC >> y) | (SRC << (64-y)); FI; Flags Affected None Intel C/C++ Compiler Intrinsic Equivalent Auto-generated from high-level language. SIMD Floating-Point Exceptions None Other Exceptions See Table2-29, “Type 13 Class Exception Conditions”. Opcode/ Instruction Op/ En 64/32 -bit Mode CPUID Feature Flag Description VEX.LZ.F2.0F3A.W0 F0 /r ib RORX r32, r/m32, imm8 RMIV/VBMI2Rotate 32-bit r/m32 right imm8 times without affecting arithmetic flags. VEX.LZ.F2.0F3A.W1 F0 /r ib RORX r64, r/m64, imm8 RMIV/N.E.BMI2Rotate 64-bit r/m64 right imm8 times without affecting arithmetic flags. Op/EnOperand 1Operand 2Operand 3Operand 4 RMIModRM:reg (w)ModRM:r/m (r)Imm8NA This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .