image/svg+xmlRDFSBASE/RDGSBASE—Read FS/GS Segment BaseInstruction Operand EncodingDescriptionLoads the general-purpose register indicated by the modR/M:r/m field with the FS or GS segment base address.The destination operand may be either a 32-bit or a 64-bit general-purpose register. The REX.W prefix indicates the operand size is 64 bits. If no REX.W prefix is used, the operand size is 32 bits; the upper 32 bits of the source base address (for FS or GS) are ignored and upper 32 bits of the destination register are cleared. This instruction is supported only in 64-bit mode.OperationDEST := FS/GS segment base address;Flags AffectedNoneC/C++ Compiler Intrinsic EquivalentRDFSBASE:unsigned int _readfsbase_u32(void );RDFSBASE: unsigned __int64 _readfsbase_u64(void );RDGSBASE: unsigned int _readgsbase_u32(void );RDGSBASE:unsigned __int64 _readgsbase_u64(void );Protected Mode Exceptions#UD The RDFSBASE and RDGSBASE instructions are not recognized in protected mode.Real-Address Mode Exceptions#UDThe RDFSBASE and RDGSBASE instructions are not recognized in real-address mode.Virtual-8086 Mode Exceptions#UDThe RDFSBASE and RDGSBASE instructions are not recognized in virtual-8086 mode.Compatibility Mode Exceptions#UD The RDFSBASE and RDGSBASE instructions are not recognized in compatibility mode.Opcode/InstructionOp/ En64/32-bit ModeCPUID Fea-ture FlagDescriptionF3 0F AE /0RDFSBASE r32MV/IFSGSBASELoad the 32-bit destination register with the FS base address.F3 REX.W 0F AE /0RDFSBASE r64MV/IFSGSBASELoad the 64-bit destination register with the FS base address.F3 0F AE /1RDGSBASE r32MV/IFSGSBASELoad the 32-bit destination register with the GS base address.F3 REX.W 0F AE /1RDGSBASE r64MV/IFSGSBASELoad the 64-bit destination register with the GS base address.Op/EnOperand 1Operand 2Operand 3Operand 4MModRM:r/m (w)NANANA

image/svg+xml64-Bit Mode Exceptions#UD If the LOCK prefix is used.If CR4.FSGSBASE[bit 16] = 0.If CPUID.07H.0H:EBX.FSGSBASE[bit 0] = 0.

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