image/svg+xmlRCL/RCR/ROL/ROR—RotateOpcode**InstructionOp/ En64-Bit ModeCompat/Leg ModeDescriptionD0 /2RCL r/m8, 1M1Valid ValidRotate 9 bits (CF, r/m8) left once.REX + D0 /2RCL r/m8*, 1M1ValidN.E.Rotate 9 bits (CF, r/m8) left once. D2 /2RCL r/m8, CLMCValid ValidRotate 9 bits (CF, r/m8) left CL times. REX + D2 /2RCL r/m8*, CLMCValidN.E.Rotate 9 bits (CF, r/m8) left CL times. C0 /2 ibRCL r/m8, imm8MIValid ValidRotate 9 bits (CF, r/m8) left imm8 times.REX + C0 /2 ibRCL r/m8*, imm8MIValidN.E.Rotate 9 bits (CF, r/m8) left imm8 times.D1 /2RCL r/m16, 1M1Valid ValidRotate 17 bits (CF, r/m16) left once.D3 /2RCL r/m16, CLMCValid ValidRotate 17 bits (CF, r/m16) left CL times.C1 /2 ibRCL r/m16, imm8MIValid ValidRotate 17 bits (CF, r/m16) left imm8 times.D1 /2RCL r/m32, 1M1Valid ValidRotate 33 bits (CF, r/m32) left once.REX.W + D1 /2RCL r/m64, 1M1ValidN.E.Rotate 65 bits (CF, r/m64) left once. Uses a 6 bit count.D3 /2RCL r/m32, CLMCValid ValidRotate 33 bits (CF, r/m32) left CL times.REX.W + D3 /2RCL r/m64, CLMCValidN.E.Rotate 65 bits (CF, r/m64) left CL times. Uses a 6 bit count.C1 /2 ibRCL r/m32, imm8MIValid ValidRotate 33 bits (CF, r/m32) left imm8 times.REX.W + C1 /2 ibRCL r/m64, imm8MIValidN.E.Rotate 65 bits (CF, r/m64) left imm8 times. Uses a 6 bit count.D0 /3RCR r/m8, 1M1Valid ValidRotate 9 bits (CF, r/m8) right once. REX + D0 /3RCR r/m8*, 1M1ValidN.E.Rotate 9 bits (CF, r/m8) right once. D2 /3RCR r/m8, CLMCValid ValidRotate 9 bits (CF, r/m8) right CL times. REX + D2 /3RCR r/m8*, CLMCValidN.E.Rotate 9 bits (CF, r/m8) right CL times. C0 /3 ibRCR r/m8, imm8MIValid ValidRotate 9 bits (CF, r/m8) right imm8 times. REX + C0 /3 ibRCR r/m8*, imm8MIValidN.E.Rotate 9 bits (CF, r/m8) right imm8 times. D1 /3RCR r/m16, 1M1Valid ValidRotate 17 bits (CF, r/m16) right once.D3 /3RCR r/m16, CLMCValid ValidRotate 17 bits (CF, r/m16) right CL times.C1 /3 ibRCR r/m16, imm8MIValid ValidRotate 17 bits (CF, r/m16) right imm8 times.D1 /3RCR r/m32, 1M1Valid ValidRotate 33 bits (CF, r/m32) right once. Uses a 6 bit count.REX.W + D1 /3RCR r/m64, 1M1ValidN.E.Rotate 65 bits (CF, r/m64) right once. Uses a 6 bit count.D3 /3RCR r/m32, CLMCValid ValidRotate 33 bits (CF, r/m32) right CL times.REX.W + D3 /3RCR r/m64, CLMCValidN.E.Rotate 65 bits (CF, r/m64) right CL times. Uses a 6 bit count.C1 /3 ibRCR r/m32, imm8MIValid ValidRotate 33 bits (CF, r/m32) right imm8 times.REX.W + C1 /3 ibRCR r/m64, imm8MIValidN.E.Rotate 65 bits (CF, r/m64) right imm8 times. Uses a 6 bit count.D0 /0ROL r/m8, 1M1Valid ValidRotate 8 bits r/m8 left once.REX + D0 /0ROL r/m8*, 1M1ValidN.E.Rotate 8 bits r/m8 left onceD2 /0ROL r/m8, CLMCValid ValidRotate 8 bits r/m8 left CL times.REX + D2 /0ROL r/m8*, CLMCValidN.E.Rotate 8 bits r/m8 left CL times.C0 /0 ibROL r/m8, imm8MIValid ValidRotate 8 bits r/m8 left imm8 times.

image/svg+xmlInstruction Operand EncodingOpcode**InstructionOp/ En64-Bit ModeCompat/Leg ModeDescriptionREX + C0 /0 ibROL r/m8*, imm8MIValidN.E.Rotate 8 bits r/m8 left imm8 times.D1 /0ROL r/m16, 1M1Valid ValidRotate 16 bits r/m16 left once.D3 /0ROL r/m16, CLMCValid ValidRotate 16 bits r/m16 left CL times.C1 /0 ibROL r/m16, imm8MIValid ValidRotate 16 bits r/m16 left imm8 times.D1 /0ROL r/m32, 1M1Valid ValidRotate 32 bits r/m32 left once.REX.W + D1 /0ROL r/m64, 1M1ValidN.E.Rotate 64 bits r/m64 left once. Uses a 6 bit count.D3 /0ROL r/m32, CLMCValid ValidRotate 32 bits r/m32 left CL times.REX.W + D3 /0ROL r/m64, CLMCValidN.E.Rotate 64 bits r/m64 left CL times. Uses a 6 bit count.C1 /0 ibROL r/m32, imm8MIValid ValidRotate 32 bits r/m32 left imm8 times.REX.W + C1 /0 ibROL r/m64, imm8MIValidN.E.Rotate 64 bits r/m64 left imm8 times. Uses a 6 bit count.D0 /1ROR r/m8, 1M1Valid ValidRotate 8 bits r/m8 right once.REX + D0 /1ROR r/m8*, 1M1ValidN.E.Rotate 8 bits r/m8 right once.D2 /1ROR r/m8, CLMCValid ValidRotate 8 bits r/m8 right CL times.REX + D2 /1ROR r/m8*, CLMCValidN.E.Rotate 8 bits r/m8 right CL times.C0 /1 ibROR r/m8, imm8MIValid ValidRotate 8 bits r/m16 right imm8 times.REX + C0 /1 ibROR r/m8*, imm8MIValidN.E.Rotate 8 bits r/m16 right imm8 times.D1 /1ROR r/m16, 1M1Valid ValidRotate 16 bits r/m16 right once.D3 /1ROR r/m16, CLMCValid ValidRotate 16 bits r/m16 right CL times.C1 /1 ibROR r/m16, imm8MIValid ValidRotate 16 bits r/m16 right imm8 times.D1 /1ROR r/m32, 1M1Valid ValidRotate 32 bits r/m32 right once.REX.W + D1 /1ROR r/m64, 1M1ValidN.E.Rotate 64 bits r/m64 right once. Uses a 6 bit count.D3 /1ROR r/m32, CLMCValid ValidRotate 32 bits r/m32 right CL times.REX.W + D3 /1ROR r/m64, CLMCValidN.E.Rotate 64 bits r/m64 right CL times. Uses a 6 bit count.C1 /1 ibROR r/m32, imm8MIValid ValidRotate 32 bits r/m32 right imm8 times.REX.W + C1 /1 ibROR r/m64, imm8MIValid N.E.Rotate 64 bits r/m64 right imm8 times. Uses a 6 bit count.NOTES:*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.**See IA-32 Architecture Compatibility section below.Op/EnOperand 1Operand 2Operand 3Operand 4M1ModRM:r/m (w)1NANAMCModRM:r/m (w)CLNANAMIModRM:r/m (w)imm8NANA

image/svg+xmlDescriptionShifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the second operand (count operand) and stores the result in the destination operand. The destination operand can be a register or a memory location; the count operand is an unsigned integer that can be an immediate or a value in the CL register. The count is masked to 5 bits (or 6 bits if in 64-bit mode and REX.W = 1).The rotate left (ROL) and rotate through carry left (RCL) instructions shift all the bits toward more-significant bit positions, except for the most-significant bit, which is rotated to the least-significant bit location. The rotate right (ROR) and rotate through carry right (RCR) instructions shift all the bits toward less significant bit positions, except for the least-significant bit, which is rotated to the most-significant bit location.The RCL and RCR instructions include the CF flag in the rotation. The RCL instruction shifts the CF flag into the least-significant bit and shifts the most-significant bit into the CF flag. The RCR instruction shifts the CF flag into the most-significant bit and shifts the least-significant bit into the CF flag. For the ROL and ROR instructions, the orig-inal value of the CF flag is not a part of the result, but the CF flag receives a copy of the bit that was shifted from one end to the other.The OF flag is defined only for the 1-bit rotates; it is undefined in all other cases (except RCL and RCR instructions only: a zero-bit rotate does nothing, that is affects no flags). For left rotates, the OF flag is set to the exclusive OR of the CF bit (after the rotate) and the most-significant bit of the result. For right rotates, the OF flag is set to the exclusive OR of the two most-significant bits of the result.In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Use of REX.W promotes the first operand to 64 bits and causes the count operand to become a 6-bit counter.IA-32 Architecture CompatibilityThe 8086 does not mask the rotation count. However, all other IA-32 processors (starting with the Intel 286 processor) do mask the rotation count to 5 bits, resulting in a maximum count of 31. This masking is done in all operating modes (including the virtual-8086 mode) to reduce the maximum execution time of the instructions.Operation(* RCL and RCR instructions *)SIZE := OperandSize;CASE (determine count) OFSIZE := 8:tempCOUNT := (COUNT AND 1FH) MOD 9;SIZE := 16:tempCOUNT := (COUNT AND 1FH) MOD 17;SIZE := 32:tempCOUNT := COUNT AND 1FH;SIZE := 64:tempCOUNT := COUNT AND 3FH;ESAC;(* RCL instruction operation *)WHILE (tempCOUNT ≠ 0)DOtempCF := MSB(DEST);DEST := (DEST ∗ 2) + CF;CF := tempCF;tempCOUNT := tempCOUNT – 1;OD;ELIHW;IF (COUNT & COUNTMASK) = 1THEN OF := MSB(DEST) XOR CF;ELSE OF is undefined;FI;

image/svg+xml(* RCR instruction operation *)IF (COUNT & COUNTMASK) = 1THEN OF := MSB(DEST) XOR CF;ELSE OF is undefined;FI;WHILE (tempCOUNT ≠ 0)DOtempCF := LSB(SRC);DEST := (DEST / 2) + (CF * 2SIZE);CF := tempCF;tempCOUNT := tempCOUNT – 1;OD;(* ROL and ROR instructions *)IF OperandSize = 64THEN COUNTMASK = 3FH;ELSE COUNTMASK = 1FH;FI;(* ROL instruction operation *)tempCOUNT := (COUNT & COUNTMASK) MOD SIZEWHILE (tempCOUNT ≠ 0)DOtempCF := MSB(DEST);DEST := (DEST ∗ 2) + tempCF;tempCOUNT := tempCOUNT – 1;OD;ELIHW;IF (COUNT & COUNTMASK) ≠ 0THEN CF := LSB(DEST);FI;IF (COUNT & COUNTMASK) = 1THEN OF := MSB(DEST) XOR CF;ELSE OF is undefined;FI;(* ROR instruction operation *)tempCOUNT := (COUNT & COUNTMASK) MOD SIZEWHILE (tempCOUNT ≠ 0)DOtempCF := LSB(SRC);DEST := (DEST / 2) + (tempCF ∗ 2SIZE);tempCOUNT := tempCOUNT – 1;OD;ELIHW;IF (COUNT & COUNTMASK) ≠ 0THEN CF := MSB(DEST);FI;IF (COUNT & COUNTMASK) = 1THEN OF := MSB(DEST) XOR MSB − 1(DEST);ELSE OF is undefined;FI;

image/svg+xmlFlags AffectedIf the masked count is 0, the flags are not affected. If the masked count is 1, then the OF flag is affected, otherwise (masked count is greater than 1) the OF flag is undefined. The CF flag is affected when the masked count is non-zero. The SF, ZF, AF, and PF flags are always unaffected.Protected Mode Exceptions#GP(0)If the source operand is located in a non-writable segment.If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made.#UD If the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the source operand is located in a nonwritable segment.If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.