PSIGNB/PSIGNW/PSIGND — Packed SIGN Instruction Operand EncodingOpcode/InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F 38 08 /r1PSIGNB mm1, mm2/m64RMV/VSSSE3Negate/zero/preserve packed byte integers in mm1 depending on the corresponding sign in mm2/m64.66 0F 38 08 /r PSIGNB xmm1, xmm2/m128RMV/VSSSE3Negate/zero/preserve packed byte integers in xmm1 depending on the corresponding sign in xmm2/m128.NP 0F 38 09 /r1PSIGNW mm1, mm2/m64RMV/VSSSE3Negate/zero/preserve packed word integers in mm1 depending on the corresponding sign in mm2/m128.66 0F 38 09 /r PSIGNW xmm1, xmm2/m128RMV/VSSSE3Negate/zero/preserve packed word integers in xmm1 depending on the corresponding sign in xmm2/m128.NP 0F 38 0A /r1PSIGND mm1, mm2/m64RMV/VSSSE3Negate/zero/preserve packed doubleword integers in mm1 depending on the corresponding sign in mm2/m128.66 0F 38 0A /r PSIGND xmm1, xmm2/m128 RMV/VSSSE3Negate/zero/preserve packed doubleword integers in xmm1 depending on the corresponding sign in xmm2/m128. VEX.128.66.0F38.WIG 08 /rVPSIGNB xmm1, xmm2, xmm3/m128RVMV/VAVXNegate/zero/preserve packed byte integers in xmm2 depending on the corresponding sign in xmm3/m128.VEX.128.66.0F38.WIG 09 /rVPSIGNW xmm1, xmm2, xmm3/m128RVMV/VAVXNegate/zero/preserve packed word integers in xmm2 depending on the corresponding sign in xmm3/m128.VEX.128.66.0F38.WIG 0A /rVPSIGND xmm1, xmm2, xmm3/m128RVMV/VAVXNegate/zero/preserve packed doubleword integers in xmm2 depending on the corresponding sign in xmm3/m128.VEX.256.66.0F38.WIG 08 /rVPSIGNB ymm1, ymm2, ymm3/m256RVMV/VAVX2Negate packed byte integers in ymm2 if the corresponding sign in ymm3/m256 is less than zero.VEX.256.66.0F38.WIG 09 /rVPSIGNW ymm1, ymm2, ymm3/m256RVMV/VAVX2Negate packed 16-bit integers in ymm2 if the corresponding sign in ymm3/m256 is less than zero.VEX.256.66.0F38.WIG 0A /rVPSIGND ymm1, ymm2, ymm3/m256RVMV/VAVX2Negate packed doubleword integers in ymm2if the corresponding sign in ymm3/m256 is less than zero.NOTES:1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.Op/EnOperand 1Operand 2Operand 3Operand 4RMModRM:reg (r, w)ModRM:r/m (r)NANARVMModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NA
This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.