PSADBW—Compute Sum of Absolute DifferencesInstruction Operand EncodingOpcode/InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F F6 /r1PSADBW mm1, mm2/m64AV/VSSEComputes the absolute differences of the packed unsigned byte integers from mm2 /m64 and mm1; differences are then summed to produce an unsigned word integer result.66 0F F6 /rPSADBW xmm1, xmm2/m128AV/VSSE2Computes the absolute differences of the packed unsigned byte integers from xmm2 /m128 and xmm1; the 8 low differences and 8 high differences are then summed separately to produce two unsigned word integer results.VEX.128.66.0F.WIG F6 /rVPSADBW xmm1, xmm2, xmm3/m128BV/VAVXComputes the absolute differences of the packed unsigned byte integers from xmm3 /m128 and xmm2; the 8 low differences and 8 high differences are then summed separately to produce two unsigned word integer results.VEX.256.66.0F.WIG F6 /rVPSADBW ymm1, ymm2, ymm3/m256BV/VAVX2Computes the absolute differences of the packed unsigned byte integers from ymm3 /m256 and ymm2; then each consecutive 8 differences are summed separately to produce four unsigned word integer results.EVEX.128.66.0F.WIG F6 /rVPSADBW xmm1, xmm2, xmm3/m128CV/VAVX512VLAVX512BWComputes the absolute differences of the packed unsigned byte integers from xmm3 /m128 and xmm2; then each consecutive 8 differences are summed separately to produce two unsigned word integer results.EVEX.256.66.0F.WIG F6 /rVPSADBW ymm1, ymm2, ymm3/m256CV/VAVX512VLAVX512BWComputes the absolute differences of the packed unsigned byte integers from ymm3 /m256 and ymm2; then each consecutive 8 differences are summed separately to produce four unsigned word integer results.EVEX.512.66.0F.WIG F6 /rVPSADBW zmm1, zmm2, zmm3/m512CV/VAVX512BWComputes the absolute differences of the packed unsigned byte integers from zmm3 /m512 and zmm2; then each consecutive 8 differences are summed separately to produce eight unsigned word integer results.NOTES:1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACFull MemModRM:reg (w)EVEX.vvvvModRM:r/m (r)NA
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