image/svg+xmlPOR—Bitwise Logical ORInstruction Operand EncodingDescriptionPerforms a bitwise logical OR operation on the source operand (second operand) and the destination operand (first operand) and stores the result in the destination operand. Each bit of the result is set to 1 if either or both of the corresponding bits of the first and second operands are 1; otherwise, it is set to 0.In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).Opcode/InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F EB /r1POR mm, mm/m64AV/V MMXBitwise OR of mm/m64 and mm.66 0F EB /rPOR xmm1, xmm2/m128AV/VSSE2Bitwise OR of xmm2/m128 and xmm1.VEX.128.66.0F.WIG EB /rVPOR xmm1, xmm2, xmm3/m128BV/VAVXBitwise OR of xmm2/m128 and xmm3.VEX.256.66.0F.WIG EB /rVPOR ymm1, ymm2, ymm3/m256BV/VAVX2Bitwise OR of ymm2/m256 and ymm3.EVEX.128.66.0F.W0 EB /rVPORD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst CV/VAVX512VLAVX512FBitwise OR of packed doubleword integers in xmm2 and xmm3/m128/m32bcst using writemask k1. EVEX.256.66.0F.W0 EB /rVPORD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst CV/VAVX512VLAVX512FBitwise OR of packed doubleword integers in ymm2 and ymm3/m256/m32bcst using writemask k1. EVEX.512.66.0F.W0 EB /rVPORD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst CV/VAVX512FBitwise OR of packed doubleword integers in zmm2 and zmm3/m512/m32bcst using writemask k1. EVEX.128.66.0F.W1 EB /rVPORQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstCV/VAVX512VLAVX512FBitwise OR of packed quadword integers in xmm2 and xmm3/m128/m64bcst using writemask k1. EVEX.256.66.0F.W1 EB /rVPORQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstCV/VAVX512VLAVX512FBitwise OR of packed quadword integers in ymm2 and ymm3/m256/m64bcst using writemask k1. EVEX.512.66.0F.W1 EB /rVPORQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstCV/VAVX512FBitwise OR of packed quadword integers in zmm2 and zmm3/m512/m64bcst using writemask k1. NOTES:1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACFullModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlLegacy SSE version: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an MMX technology register.128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first source and destination operands can be XMM registers. Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first source and destination operands can be XMM registers. Bits (MAXVL-1:128) of the destination YMM register are zeroed. VEX.256 encoded version: The second source operand is an YMM register or a 256-bit memory location. The first source and destination operands can be YMM registers.EVEX encoded version: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1 at 32/64-bit granularity.OperationPOR (64-bit operand)DEST := DEST OR SRCPOR (128-bit Legacy SSE version)DEST := DEST OR SRCDEST[MAXVL-1:128] (Unmodified)VPOR (VEX.128 encoded version)DEST := SRC1 OR SRC2DEST[MAXVL-1:128] := 0VPOR (VEX.256 encoded version)DEST := SRC1 OR SRC2DEST[MAXVL-1:256] := 0VPORD (EVEX encoded versions) (KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no writemask* THENIF (EVEX.b = 1) AND (SRC2 *is memory*)THEN DEST[i+31:i] := SRC1[i+31:i] BITWISE OR SRC2[31:0]ELSE DEST[i+31:i] := SRC1[i+31:i] BITWISE OR SRC2[i+31:i]FI;ELSE IF *merging-masking*; merging-masking*DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FI;FI;ENDFOR;DEST[MAXVL-1:VL] := 0

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentVPORD __m512i _mm512_or_epi32(__m512i a, __m512i b);VPORD __m512i _mm512_mask_or_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);VPORD __m512i _mm512_maskz_or_epi32( __mmask16 k, __m512i a, __m512i b);VPORD __m256i _mm256_or_epi32(__m256i a, __m256i b);VPORD __m256i _mm256_mask_or_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b,);VPORD __m256i _mm256_maskz_or_epi32( __mmask8 k, __m256i a, __m256i b);VPORD __m128i _mm_or_epi32(__m128i a, __m128i b);VPORD __m128i _mm_mask_or_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);VPORD __m128i _mm_maskz_or_epi32( __mmask8 k, __m128i a, __m128i b);VPORQ __m512i _mm512_or_epi64(__m512i a, __m512i b);VPORQ __m512i _mm512_mask_or_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);VPORQ __m512i _mm512_maskz_or_epi64(__mmask8 k, __m512i a, __m512i b);VPORQ __m256i _mm256_or_epi64(__m256i a, int imm);VPORQ __m256i _mm256_mask_or_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);VPORQ __m256i _mm256_maskz_or_epi64( __mmask8 k, __m256i a, __m256i b);VPORQ __m128i _mm_or_epi64(__m128i a, __m128i b);VPORQ __m128i _mm_mask_or_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);VPORQ __m128i _mm_maskz_or_epi64( __mmask8 k, __m128i a, __m128i b);POR __m64 _mm_or_si64(__m64 m1, __m64 m2)(V)POR:__m128i _mm_or_si128(__m128i m1, __m128i m2)VPOR:__m256i _mm256_or_si256 ( __m256i a, __m256i b)Flags AffectedNone.SIMD Floating-Point ExceptionsNone.Other ExceptionsNon-EVEX-encoded instruction, see Table2-21, “Type 4 Class Exception Conditions”.EVEX-encoded instruction, see Table2-49, “Type E4 Class Exception Conditions”.

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