POR—Bitwise Logical ORInstruction Operand EncodingDescriptionPerforms a bitwise logical OR operation on the source operand (second operand) and the destination operand (first operand) and stores the result in the destination operand. Each bit of the result is set to 1 if either or both of the corresponding bits of the first and second operands are 1; otherwise, it is set to 0.In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).Opcode/InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F EB /r1POR mm, mm/m64AV/V MMXBitwise OR of mm/m64 and mm.66 0F EB /rPOR xmm1, xmm2/m128AV/VSSE2Bitwise OR of xmm2/m128 and xmm1.VEX.128.66.0F.WIG EB /rVPOR xmm1, xmm2, xmm3/m128BV/VAVXBitwise OR of xmm2/m128 and xmm3.VEX.256.66.0F.WIG EB /rVPOR ymm1, ymm2, ymm3/m256BV/VAVX2Bitwise OR of ymm2/m256 and ymm3.EVEX.128.66.0F.W0 EB /rVPORD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst CV/VAVX512VLAVX512FBitwise OR of packed doubleword integers in xmm2 and xmm3/m128/m32bcst using writemask k1. EVEX.256.66.0F.W0 EB /rVPORD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst CV/VAVX512VLAVX512FBitwise OR of packed doubleword integers in ymm2 and ymm3/m256/m32bcst using writemask k1. EVEX.512.66.0F.W0 EB /rVPORD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst CV/VAVX512FBitwise OR of packed doubleword integers in zmm2 and zmm3/m512/m32bcst using writemask k1. EVEX.128.66.0F.W1 EB /rVPORQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstCV/VAVX512VLAVX512FBitwise OR of packed quadword integers in xmm2 and xmm3/m128/m64bcst using writemask k1. EVEX.256.66.0F.W1 EB /rVPORQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstCV/VAVX512VLAVX512FBitwise OR of packed quadword integers in ymm2 and ymm3/m256/m64bcst using writemask k1. EVEX.512.66.0F.W1 EB /rVPORQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstCV/VAVX512FBitwise OR of packed quadword integers in zmm2 and zmm3/m512/m64bcst using writemask k1. NOTES:1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACFullModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA
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