image/svg+xmlPMULLD/PMULLQ—Multiply Packed Integers and Store Low ResultInstruction Operand EncodingDescriptionPerforms a SIMD signed multiply of the packed signed dword/qword integers from each element of the first source operand with the corresponding element in the second source operand. The low 32/64 bits of each 64/128-bit intermediate results are stored to the destination operand. 128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding ZMM destina-tion register remain unchanged.VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding ZMM register are zeroed.VEX.256 encoded version: The first source operand is a YMM register; The second source operand is a YMM register or 256-bit memory location. Bits (MAXVL-1:256) of the corresponding destination ZMM register are zeroed.Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F 38 40 /rPMULLD xmm1, xmm2/m128AV/VSSE4_1Multiply the packed dword signed integers in xmm1 and xmm2/m128 and store the low 32 bits of each product in xmm1.VEX.128.66.0F38.WIG 40 /rVPMULLD xmm1, xmm2, xmm3/m128BV/VAVXMultiply the packed dword signed integers in xmm2 and xmm3/m128 and store the low 32 bits of each product in xmm1.VEX.256.66.0F38.WIG 40 /rVPMULLD ymm1, ymm2, ymm3/m256BV/VAVX2Multiply the packed dword signed integers in ymm2 and ymm3/m256 and store the low 32 bits of each product in ymm1.EVEX.128.66.0F38.W0 40 /rVPMULLD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstCV/VAVX512VLAVX512FMultiply the packed dword signed integers in xmm2 and xmm3/m128/m32bcst and store the low 32 bits of each product in xmm1 under writemask k1.EVEX.256.66.0F38.W0 40 /rVPMULLD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstCV/VAVX512VLAVX512FMultiply the packed dword signed integers in ymm2 and ymm3/m256/m32bcst and store the low 32 bits of each product in ymm1 under writemask k1.EVEX.512.66.0F38.W0 40 /rVPMULLD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcstCV/VAVX512FMultiply the packed dword signed integers in zmm2 and zmm3/m512/m32bcst and store the low 32 bits of each product in zmm1 under writemask k1.EVEX.128.66.0F38.W1 40 /rVPMULLQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstCV/VAVX512VLAVX512DQMultiply the packed qword signed integers in xmm2 and xmm3/m128/m64bcst and store the low 64 bits of each product in xmm1 under writemask k1.EVEX.256.66.0F38.W1 40 /rVPMULLQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstCV/VAVX512VLAVX512DQMultiply the packed qword signed integers in ymm2 and ymm3/m256/m64bcst and store the low 64 bits of each product in ymm1 under writemask k1.EVEX.512.66.0F38.W1 40 /rVPMULLQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstCV/VAVX512DQMultiply the packed qword signed integers in zmm2 and zmm3/m512/m64bcst and store the low 64 bits of each product in zmm1 under writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACFullModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.OperationVPMULLQ (EVEX encoded versions)(KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64IF k1[j] OR *no writemask* THENIF (EVEX.b == 1) AND (SRC2 *is memory*)THEN Temp[127:0] := SRC1[i+63:i] * SRC2[63:0]ELSE Temp[127:0] := SRC1[i+63:i] * SRC2[i+63:i]FI;DEST[i+63:i] := Temp[63:0]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+63:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+63:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0VPMULLD (EVEX encoded versions)(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no writemask* THENIF (EVEX.b = 1) AND (SRC2 *is memory*)THEN Temp[63:0] := SRC1[i+31:i] * SRC2[31:0]ELSE Temp[63:0] := SRC1[i+31:i] * SRC2[i+31:i]FI;DEST[i+31:i] := Temp[31:0]ELSE IF *merging-masking*; merging-masking*DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0

image/svg+xmlVPMULLD (VEX.256 encoded version)Temp0[63:0] := SRC1[31:0] * SRC2[31:0]Temp1[63:0] := SRC1[63:32] * SRC2[63:32]Temp2[63:0] := SRC1[95:64] * SRC2[95:64]Temp3[63:0] := SRC1[127:96] * SRC2[127:96]Temp4[63:0] := SRC1[159:128] * SRC2[159:128]Temp5[63:0] := SRC1[191:160] * SRC2[191:160]Temp6[63:0] := SRC1[223:192] * SRC2[223:192]Temp7[63:0] := SRC1[255:224] * SRC2[255:224]DEST[31:0] := Temp0[31:0]DEST[63:32] := Temp1[31:0]DEST[95:64] := Temp2[31:0]DEST[127:96] := Temp3[31:0]DEST[159:128] := Temp4[31:0]DEST[191:160] := Temp5[31:0]DEST[223:192] := Temp6[31:0]DEST[255:224] := Temp7[31:0]DEST[MAXVL-1:256] := 0VPMULLD (VEX.128 encoded version)Temp0[63:0] := SRC1[31:0] * SRC2[31:0]Temp1[63:0] := SRC1[63:32] * SRC2[63:32]Temp2[63:0] := SRC1[95:64] * SRC2[95:64]Temp3[63:0] := SRC1[127:96] * SRC2[127:96]DEST[31:0] := Temp0[31:0]DEST[63:32] := Temp1[31:0]DEST[95:64] := Temp2[31:0]DEST[127:96] := Temp3[31:0]DEST[MAXVL-1:128] := 0PMULLD (128-bit Legacy SSE version)Temp0[63:0] := DEST[31:0] * SRC[31:0]Temp1[63:0] := DEST[63:32] * SRC[63:32]Temp2[63:0] := DEST[95:64] * SRC[95:64]Temp3[63:0] := DEST[127:96] * SRC[127:96]DEST[31:0] := Temp0[31:0]DEST[63:32] := Temp1[31:0]DEST[95:64] := Temp2[31:0]DEST[127:96] := Temp3[31:0]DEST[MAXVL-1:128] (Unmodified)Intel C/C++ Compiler Intrinsic EquivalentVPMULLD __m512i _mm512_mullo_epi32(__m512i a, __m512i b);VPMULLD __m512i _mm512_mask_mullo_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);VPMULLD __m512i _mm512_maskz_mullo_epi32( __mmask16 k, __m512i a, __m512i b);VPMULLD __m256i _mm256_mask_mullo_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);VPMULLD __m256i _mm256_maskz_mullo_epi32( __mmask8 k, __m256i a, __m256i b);VPMULLD __m128i _mm_mask_mullo_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);VPMULLD __m128i _mm_maskz_mullo_epi32( __mmask8 k, __m128i a, __m128i b);VPMULLD __m256i _mm256_mullo_epi32(__m256i a, __m256i b);PMULLD __m128i _mm_mullo_epi32(__m128i a, __m128i b);VPMULLQ __m512i _mm512_mullo_epi64(__m512i a, __m512i b);VPMULLQ __m512i _mm512_mask_mullo_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);

image/svg+xmlVPMULLQ __m512i _mm512_maskz_mullo_epi64( __mmask8 k, __m512i a, __m512i b);VPMULLQ __m256i _mm256_mullo_epi64(__m256i a, __m256i b);VPMULLQ __m256i _mm256_mask_mullo_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);VPMULLQ __m256i _mm256_maskz_mullo_epi64( __mmask8 k, __m256i a, __m256i b);VPMULLQ __m128i _mm_mullo_epi64(__m128i a, __m128i b);VPMULLQ __m128i _mm_mask_mullo_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);VPMULLQ __m128i _mm_maskz_mullo_epi64( __mmask8 k, __m128i a, __m128i b);SIMD Floating-Point ExceptionsNoneOther ExceptionsNon-EVEX-encoded instruction, see Table2-21, “Type 4 Class Exception Conditions”.EVEX-encoded instruction, see Table2-49, “Type E4 Class Exception Conditions”.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.