PMULLD/PMULLQ—Multiply Packed Integers and Store Low ResultInstruction Operand EncodingDescriptionPerforms a SIMD signed multiply of the packed signed dword/qword integers from each element of the first source operand with the corresponding element in the second source operand. The low 32/64 bits of each 64/128-bit intermediate results are stored to the destination operand. 128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding ZMM destina-tion register remain unchanged.VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding ZMM register are zeroed.VEX.256 encoded version: The first source operand is a YMM register; The second source operand is a YMM register or 256-bit memory location. Bits (MAXVL-1:256) of the corresponding destination ZMM register are zeroed.Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F 38 40 /rPMULLD xmm1, xmm2/m128AV/VSSE4_1Multiply the packed dword signed integers in xmm1 and xmm2/m128 and store the low 32 bits of each product in xmm1.VEX.128.66.0F38.WIG 40 /rVPMULLD xmm1, xmm2, xmm3/m128BV/VAVXMultiply the packed dword signed integers in xmm2 and xmm3/m128 and store the low 32 bits of each product in xmm1.VEX.256.66.0F38.WIG 40 /rVPMULLD ymm1, ymm2, ymm3/m256BV/VAVX2Multiply the packed dword signed integers in ymm2 and ymm3/m256 and store the low 32 bits of each product in ymm1.EVEX.128.66.0F38.W0 40 /rVPMULLD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstCV/VAVX512VLAVX512FMultiply the packed dword signed integers in xmm2 and xmm3/m128/m32bcst and store the low 32 bits of each product in xmm1 under writemask k1.EVEX.256.66.0F38.W0 40 /rVPMULLD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstCV/VAVX512VLAVX512FMultiply the packed dword signed integers in ymm2 and ymm3/m256/m32bcst and store the low 32 bits of each product in ymm1 under writemask k1.EVEX.512.66.0F38.W0 40 /rVPMULLD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcstCV/VAVX512FMultiply the packed dword signed integers in zmm2 and zmm3/m512/m32bcst and store the low 32 bits of each product in zmm1 under writemask k1.EVEX.128.66.0F38.W1 40 /rVPMULLQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstCV/VAVX512VLAVX512DQMultiply the packed qword signed integers in xmm2 and xmm3/m128/m64bcst and store the low 64 bits of each product in xmm1 under writemask k1.EVEX.256.66.0F38.W1 40 /rVPMULLQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstCV/VAVX512VLAVX512DQMultiply the packed qword signed integers in ymm2 and ymm3/m256/m64bcst and store the low 64 bits of each product in ymm1 under writemask k1.EVEX.512.66.0F38.W1 40 /rVPMULLQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstCV/VAVX512DQMultiply the packed qword signed integers in zmm2 and zmm3/m512/m64bcst and store the low 64 bits of each product in zmm1 under writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACFullModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA
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