image/svg+xmlPMULHUW—Multiply Packed Unsigned Integers and Store High ResultInstruction Operand EncodingDescriptionPerforms a SIMD unsigned multiply of the packed unsigned word integers in the destination operand (first operand) and the source operand (second operand), and stores the high 16 bits of each 32-bit intermediate results in the destination operand. (Figure4-12 shows this operation when using 64-bit operands.)In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).Legacy SSE version 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an MMX technology register.128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destina-tion register remain unchanged.Opcode/InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F E4 /r1PMULHUW mm1, mm2/m64AV/VSSEMultiply the packed unsigned word integers in mm1 register and mm2/m64, and store the high 16 bits of the results in mm1. 66 0F E4 /rPMULHUW xmm1, xmm2/m128AV/VSSE2Multiply the packed unsigned word integers in xmm1 and xmm2/m128, and store the high 16 bits of the results in xmm1.VEX.128.66.0F.WIG E4 /rVPMULHUW xmm1, xmm2, xmm3/m128BV/VAVXMultiply the packed unsigned word integers in xmm2 and xmm3/m128, and store the high 16 bits of the results in xmm1.VEX.256.66.0F.WIG E4 /rVPMULHUW ymm1, ymm2, ymm3/m256BV/VAVX2Multiply the packed unsigned word integers in ymm2 and ymm3/m256, and store the high 16 bits of the results in ymm1.EVEX.128.66.0F.WIG E4 /rVPMULHUW xmm1 {k1}{z}, xmm2, xmm3/m128CV/VAVX512VLAVX512BWMultiply the packed unsigned word integers in xmm2 and xmm3/m128, and store the high 16 bits of the results in xmm1 under writemask k1.EVEX.256.66.0F.WIG E4 /rVPMULHUW ymm1 {k1}{z}, ymm2, ymm3/m256CV/VAVX512VLAVX512BWMultiply the packed unsigned word integers in ymm2 and ymm3/m256, and store the high 16 bits of the results in ymm1 under writemask k1.EVEX.512.66.0F.WIG E4 /rVPMULHUW zmm1 {k1}{z}, zmm2, zmm3/m512CV/VAVX512BWMultiply the packed unsigned word integers in zmm2 and zmm3/m512, and store the high 16 bits of the results in zmm1 under writemask k1.NOTES:1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACFull MemModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlVEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are zeroed. VEX.L must be 0, otherwise the instruction will #UD.VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The first source and destination operands are YMM registers.EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.OperationPMULHUW (with 64-bit operands)TEMP0[31:0] := DEST[15:0] ∗ SRC[15:0]; (* Unsigned multiplication *)TEMP1[31:0] := DEST[31:16] ∗ SRC[31:16];TEMP2[31:0] := DEST[47:32] ∗ SRC[47:32];TEMP3[31:0] := DEST[63:48] ∗ SRC[63:48];DEST[15:0] := TEMP0[31:16];DEST[31:16] := TEMP1[31:16];DEST[47:32] := TEMP2[31:16];DEST[63:48] := TEMP3[31:16];PMULHUW (with 128-bit operands)TEMP0[31:0] := DEST[15:0] ∗ SRC[15:0]; (* Unsigned multiplication *)TEMP1[31:0] := DEST[31:16] ∗ SRC[31:16];TEMP2[31:0] := DEST[47:32] ∗ SRC[47:32];TEMP3[31:0] := DEST[63:48] ∗ SRC[63:48];TEMP4[31:0] := DEST[79:64] ∗ SRC[79:64];TEMP5[31:0] := DEST[95:80] ∗ SRC[95:80];TEMP6[31:0] := DEST[111:96] ∗ SRC[111:96];TEMP7[31:0] := DEST[127:112] ∗ SRC[127:112];DEST[15:0] := TEMP0[31:16];DEST[31:16] := TEMP1[31:16];DEST[47:32] := TEMP2[31:16];DEST[63:48] := TEMP3[31:16];DEST[79:64] := TEMP4[31:16];DEST[95:80] := TEMP5[31:16];DEST[111:96] := TEMP6[31:16];DEST[127:112] := TEMP7[31:16];Figure 4-12. PMULHUW and PMULHW Instruction Operation Using 64-bit OperandsX3X2X1X0Z3 = X3 ∗ Y3Z2 = X2 ∗ Y2Z1 = X1 ∗ Y1Z0 = X0 ∗ Y0SRCDESTDESTY3Y2Y1Y0TEMPZ3[31:16]Z2[31:16]Z1[31:16]Z0[31:16]

image/svg+xmlVPMULHUW (VEX.128 encoded version)TEMP0[31:0] := SRC1[15:0] * SRC2[15:0]TEMP1[31:0] := SRC1[31:16] * SRC2[31:16]TEMP2[31:0] := SRC1[47:32] * SRC2[47:32]TEMP3[31:0] := SRC1[63:48] * SRC2[63:48]TEMP4[31:0] := SRC1[79:64] * SRC2[79:64]TEMP5[31:0] := SRC1[95:80] * SRC2[95:80]TEMP6[31:0] := SRC1[111:96] * SRC2[111:96]TEMP7[31:0] := SRC1[127:112] * SRC2[127:112]DEST[15:0] := TEMP0[31:16]DEST[31:16] := TEMP1[31:16]DEST[47:32] := TEMP2[31:16]DEST[63:48] := TEMP3[31:16]DEST[79:64] := TEMP4[31:16]DEST[95:80] := TEMP5[31:16]DEST[111:96] := TEMP6[31:16]DEST[127:112] := TEMP7[31:16]DEST[MAXVL-1:128] := 0PMULHUW (VEX.256 encoded version)TEMP0[31:0] := SRC1[15:0] * SRC2[15:0]TEMP1[31:0] := SRC1[31:16] * SRC2[31:16]TEMP2[31:0] := SRC1[47:32] * SRC2[47:32]TEMP3[31:0] := SRC1[63:48] * SRC2[63:48]TEMP4[31:0] := SRC1[79:64] * SRC2[79:64]TEMP5[31:0] := SRC1[95:80] * SRC2[95:80]TEMP6[31:0] := SRC1[111:96] * SRC2[111:96]TEMP7[31:0] := SRC1[127:112] * SRC2[127:112]TEMP8[31:0] := SRC1[143:128] * SRC2[143:128]TEMP9[31:0] := SRC1[159:144] * SRC2[159:144]TEMP10[31:0] := SRC1[175:160] * SRC2[175:160]TEMP11[31:0] := SRC1[191:176] * SRC2[191:176]TEMP12[31:0] := SRC1[207:192] * SRC2[207:192]TEMP13[31:0] := SRC1[223:208] * SRC2[223:208]TEMP14[31:0] := SRC1[239:224] * SRC2[239:224]TEMP15[31:0] := SRC1[255:240] * SRC2[255:240]DEST[15:0] := TEMP0[31:16]DEST[31:16] := TEMP1[31:16]DEST[47:32] := TEMP2[31:16]DEST[63:48] := TEMP3[31:16]DEST[79:64] := TEMP4[31:16]DEST[95:80] := TEMP5[31:16]DEST[111:96] := TEMP6[31:16]DEST[127:112] := TEMP7[31:16]DEST[143:128] := TEMP8[31:16]DEST[159:144] := TEMP9[31:16]DEST[175:160] := TEMP10[31:16]DEST[191:176] := TEMP11[31:16]DEST[207:192] := TEMP12[31:16]DEST[223:208] := TEMP13[31:16]DEST[239:224] := TEMP14[31:16]DEST[255:240] := TEMP15[31:16]DEST[MAXVL-1:256] := 0

image/svg+xmlPMULHUW (EVEX encoded versions)(KL, VL) = (8, 128), (16, 256), (32, 512)FOR j := 0 TO KL-1i := j * 16IF k1[j] OR *no writemask*THEN temp[31:0] := SRC1[i+15:i] * SRC2[i+15:i]DEST[i+15:i] := tmp[31:16]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+15:i] remains unchanged*ELSE *zeroing-masking*; zeroing-maskingDEST[i+15:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0Intel C/C++ Compiler Intrinsic EquivalentVPMULHUW __m512i _mm512_mulhi_epu16(__m512i a, __m512i b);VPMULHUW __m512i _mm512_mask_mulhi_epu16(__m512i s, __mmask32 k, __m512i a, __m512i b);VPMULHUW __m512i _mm512_maskz_mulhi_epu16( __mmask32 k, __m512i a, __m512i b);VPMULHUW __m256i _mm256_mask_mulhi_epu16(__m256i s, __mmask16 k, __m256i a, __m256i b);VPMULHUW __m256i _mm256_maskz_mulhi_epu16( __mmask16 k, __m256i a, __m256i b);VPMULHUW __m128i _mm_mask_mulhi_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);VPMULHUW __m128i _mm_maskz_mulhi_epu16( __mmask8 k, __m128i a, __m128i b);PMULHUW:__m64 _mm_mulhi_pu16(__m64 a, __m64 b)(V)PMULHUW:__m128i _mm_mulhi_epu16 ( __m128i a, __m128i b)VPMULHUW:__m256i _mm256_mulhi_epu16 ( __m256i a, __m256i b)Flags AffectedNone.Numeric ExceptionsNone.Other ExceptionsNon-EVEX-encoded instruction, see Table2-21, “Type 4 Class Exception Conditions”.EVEX-encoded instruction, see Exceptions Type E4.nb in Table2-49, “Type E4 Class Exception Conditions”.

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