PMULHRSW — Packed Multiply High with Round and Scale Instruction Operand EncodingDescription PMULHRSW multiplies vertically each signed 16-bit integer from the destination operand (first operand) with the corresponding signed 16-bit integer of the source operand (second operand), producing intermediate, signed 32-bit integers. Each intermediate 32-bit integer is truncated to the 18 most significant bits. Rounding is always performed by adding 1 to the least significant bit of the 18-bit intermediate result. The final result is obtained by selecting the 16 bits immediately to the right of the most significant bit of each 18-bit intermediate result and packed to the destination operand. When the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. In 64-bit mode and not encoded with VEX/EVEX, use the REX prefix to access XMM8-XMM15 registers. Legacy SSE version 64-bit operand: Both operands can be MMX registers. The second source operand is an MMX register or a 64-bit memory location.Opcode/InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F 38 0B /r1PMULHRSW mm1, mm2/m64AV/VSSSE3Multiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to mm1.66 0F 38 0B /rPMULHRSW xmm1, xmm2/m128 AV/VSSSE3Multiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to xmm1.VEX.128.66.0F38.WIG 0B /rVPMULHRSW xmm1, xmm2, xmm3/m128BV/VAVXMultiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to xmm1.VEX.256.66.0F38.WIG 0B /rVPMULHRSW ymm1, ymm2, ymm3/m256BV/VAVX2Multiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to ymm1.EVEX.128.66.0F38.WIG 0B /rVPMULHRSW xmm1 {k1}{z}, xmm2, xmm3/m128CV/VAVX512VLAVX512BWMultiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to xmm1 under writemask k1.EVEX.256.66.0F38.WIG 0B /rVPMULHRSW ymm1 {k1}{z}, ymm2, ymm3/m256CV/VAVX512VLAVX512BWMultiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to ymm1 under writemask k1.EVEX.512.66.0F38.WIG 0B /rVPMULHRSW zmm1 {k1}{z}, zmm2, zmm3/m512CV/VAVX512BWMultiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to zmm1 under writemask k1.NOTES:1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACFull MemModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA
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