image/svg+xmlPMULHRSW — Packed Multiply High with Round and Scale Instruction Operand EncodingDescription PMULHRSW multiplies vertically each signed 16-bit integer from the destination operand (first operand) with the corresponding signed 16-bit integer of the source operand (second operand), producing intermediate, signed 32-bit integers. Each intermediate 32-bit integer is truncated to the 18 most significant bits. Rounding is always performed by adding 1 to the least significant bit of the 18-bit intermediate result. The final result is obtained by selecting the 16 bits immediately to the right of the most significant bit of each 18-bit intermediate result and packed to the destination operand. When the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. In 64-bit mode and not encoded with VEX/EVEX, use the REX prefix to access XMM8-XMM15 registers. Legacy SSE version 64-bit operand: Both operands can be MMX registers. The second source operand is an MMX register or a 64-bit memory location.Opcode/InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F 38 0B /r1 PMULHRSW mm1, mm2/m64AV/VSSSE3Multiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to mm1.66 0F 38 0B /rPMULHRSW xmm1, xmm2/m128 AV/VSSSE3Multiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to xmm1.VEX.128.66.0F38.WIG 0B /rVPMULHRSW xmm1, xmm2, xmm3/m128BV/VAVXMultiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to xmm1.VEX.256.66.0F38.WIG 0B /rVPMULHRSW ymm1, ymm2, ymm3/m256BV/VAVX2Multiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to ymm1.EVEX.128.66.0F38.WIG 0B /rVPMULHRSW xmm1 {k1}{z}, xmm2, xmm3/m128CV/VAVX512VLAVX512BWMultiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to xmm1 under writemask k1.EVEX.256.66.0F38.WIG 0B /rVPMULHRSW ymm1 {k1}{z}, ymm2, ymm3/m256CV/VAVX512VLAVX512BWMultiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to ymm1 under writemask k1.EVEX.512.66.0F38.WIG 0B /rVPMULHRSW zmm1 {k1}{z}, zmm2, zmm3/m512CV/VAVX512BWMultiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to zmm1 under writemask k1.NOTES:1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACFull MemModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xml128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destina-tion register remain unchanged.VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are zeroed. VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The first source and destination operands are YMM registers.EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.OperationPMULHRSW (with 64-bit operands)temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) >>14) + 1;temp1[31:0] = INT32 ((DEST[31:16] * SRC[31:16]) >>14) + 1;temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) >> 14) + 1;temp3[31:0] = INT32 ((DEST[63:48] * SRc[63:48]) >> 14) + 1;DEST[15:0] = temp0[16:1];DEST[31:16] = temp1[16:1];DEST[47:32] = temp2[16:1];DEST[63:48] = temp3[16:1];PMULHRSW (with 128-bit operand)temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) >>14) + 1;temp1[31:0] = INT32 ((DEST[31:16] * SRC[31:16]) >>14) + 1;temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) >>14) + 1;temp3[31:0] = INT32 ((DEST[63:48] * SRC[63:48]) >>14) + 1;temp4[31:0] = INT32 ((DEST[79:64] * SRC[79:64]) >>14) + 1;temp5[31:0] = INT32 ((DEST[95:80] * SRC[95:80]) >>14) + 1;temp6[31:0] = INT32 ((DEST[111:96] * SRC[111:96]) >>14) + 1;temp7[31:0] = INT32 ((DEST[127:112] * SRC[127:112) >>14) + 1;DEST[15:0] = temp0[16:1];DEST[31:16] = temp1[16:1];DEST[47:32] = temp2[16:1];DEST[63:48] = temp3[16:1];DEST[79:64] = temp4[16:1];DEST[95:80] = temp5[16:1];DEST[111:96] = temp6[16:1];DEST[127:112] = temp7[16:1];VPMULHRSW (VEX.128 encoded version)temp0[31:0] := INT32 ((SRC1[15:0] * SRC2[15:0]) >>14) + 1temp1[31:0] := INT32 ((SRC1[31:16] * SRC2[31:16]) >>14) + 1temp2[31:0] := INT32 ((SRC1[47:32] * SRC2[47:32]) >>14) + 1temp3[31:0] := INT32 ((SRC1[63:48] * SRC2[63:48]) >>14) + 1temp4[31:0] := INT32 ((SRC1[79:64] * SRC2[79:64]) >>14) + 1temp5[31:0] := INT32 ((SRC1[95:80] * SRC2[95:80]) >>14) + 1temp6[31:0] := INT32 ((SRC1[111:96] * SRC2[111:96]) >>14) + 1temp7[31:0] := INT32 ((SRC1[127:112] * SRC2[127:112) >>14) + 1DEST[15:0] := temp0[16:1]DEST[31:16] := temp1[16:1]DEST[47:32] := temp2[16:1]

image/svg+xmlDEST[63:48] := temp3[16:1]DEST[79:64] := temp4[16:1]DEST[95:80] := temp5[16:1]DEST[111:96] := temp6[16:1]DEST[127:112] := temp7[16:1]DEST[MAXVL-1:128] := 0VPMULHRSW (VEX.256 encoded version)temp0[31:0] := INT32 ((SRC1[15:0] * SRC2[15:0]) >>14) + 1temp1[31:0] := INT32 ((SRC1[31:16] * SRC2[31:16]) >>14) + 1temp2[31:0] := INT32 ((SRC1[47:32] * SRC2[47:32]) >>14) + 1temp3[31:0] := INT32 ((SRC1[63:48] * SRC2[63:48]) >>14) + 1temp4[31:0] := INT32 ((SRC1[79:64] * SRC2[79:64]) >>14) + 1temp5[31:0] := INT32 ((SRC1[95:80] * SRC2[95:80]) >>14) + 1temp6[31:0] := INT32 ((SRC1[111:96] * SRC2[111:96]) >>14) + 1temp7[31:0] := INT32 ((SRC1[127:112] * SRC2[127:112) >>14) + 1temp8[31:0] := INT32 ((SRC1[143:128] * SRC2[143:128]) >>14) + 1temp9[31:0] := INT32 ((SRC1[159:144] * SRC2[159:144]) >>14) + 1temp10[31:0] := INT32 ((SRC1[75:160] * SRC2[175:160]) >>14) + 1temp11[31:0] := INT32 ((SRC1[191:176] * SRC2[191:176]) >>14) + 1temp12[31:0] := INT32 ((SRC1[207:192] * SRC2[207:192]) >>14) + 1temp13[31:0] := INT32 ((SRC1[223:208] * SRC2[223:208]) >>14) + 1temp14[31:0] := INT32 ((SRC1[239:224] * SRC2[239:224]) >>14) + 1temp15[31:0] := INT32 ((SRC1[255:240] * SRC2[255:240) >>14) + 1DEST[15:0] := temp0[16:1]DEST[31:16] := temp1[16:1]DEST[47:32] := temp2[16:1]DEST[63:48] := temp3[16:1]DEST[79:64] := temp4[16:1]DEST[95:80] := temp5[16:1]DEST[111:96] := temp6[16:1]DEST[127:112] := temp7[16:1]DEST[143:128] := temp8[16:1]DEST[159:144] := temp9[16:1]DEST[175:160] := temp10[16:1]DEST[191:176] := temp11[16:1]DEST[207:192] := temp12[16:1]DEST[223:208] := temp13[16:1]DEST[239:224] := temp14[16:1]DEST[255:240] := temp15[16:1]DEST[MAXVL-1:256] := 0VPMULHRSW (EVEX encoded version)(KL, VL) = (8, 128), (16, 256), (32, 512)FOR j := 0 TO KL-1i := j * 16IF k1[j] OR *no writemask*THEN temp[31:0] := ((SRC1[i+15:i] * SRC2[i+15:i]) >>14) + 1DEST[i+15:i] := tmp[16:1]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+15:i] remains unchanged*

image/svg+xmlELSE *zeroing-masking*; zeroing-maskingDEST[i+15:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0Intel C/C++ Compiler Intrinsic EquivalentsVPMULHRSW __m512i _mm512_mulhrs_epi16(__m512i a, __m512i b);VPMULHRSW __m512i _mm512_mask_mulhrs_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);VPMULHRSW __m512i _mm512_maskz_mulhrs_epi16( __mmask32 k, __m512i a, __m512i b);VPMULHRSW __m256i _mm256_mask_mulhrs_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);VPMULHRSW __m256i _mm256_maskz_mulhrs_epi16( __mmask16 k, __m256i a, __m256i b);VPMULHRSW __m128i _mm_mask_mulhrs_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);VPMULHRSW __m128i _mm_maskz_mulhrs_epi16( __mmask8 k, __m128i a, __m128i b);PMULHRSW: __m64 _mm_mulhrs_pi16 (__m64 a, __m64 b)(V)PMULHRSW: __m128i _mm_mulhrs_epi16 (__m128i a, __m128i b)VPMULHRSW:__m256i _mm256_mulhrs_epi16 (__m256i a, __m256i b)SIMD Floating-Point ExceptionsNone.Other ExceptionsNon-EVEX-encoded instruction, see Table2-21, “Type 4 Class Exception Conditions”.EVEX-encoded instruction, see Exceptions Type E4.nb in Table2-49, “Type E4 Class Exception Conditions”.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.