image/svg+xmlPMINSB/PMINSW—Minimum of Packed Signed IntegersInstruction Operand EncodingOpcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F EA /r1PMINSW mm1, mm2/m64AV/VSSECompare signed word integers in mm2/m64 and mm1 and return minimum values.66 0F 38 38 /rPMINSB xmm1, xmm2/m128AV/VSSE4_1Compare packed signed byte integers in xmm1 and xmm2/m128 and store packed minimum values in xmm1.66 0F EA /rPMINSW xmm1, xmm2/m128AV/VSSE2Compare packed signed word integers in xmm2/m128 and xmm1 and store packed minimum values in xmm1.VEX.128.66.0F38 38 /rVPMINSB xmm1, xmm2, xmm3/m128BV/VAVXCompare packed signed byte integers in xmm2 and xmm3/m128 and store packed minimum values in xmm1.VEX.128.66.0F EA /rVPMINSW xmm1, xmm2, xmm3/m128BV/VAVXCompare packed signed word integers in xmm3/m128 and xmm2 and return packed minimum values in xmm1.VEX.256.66.0F38 38 /rVPMINSB ymm1, ymm2, ymm3/m256BV/VAVX2Compare packed signed byte integers in ymm2 and ymm3/m256 and store packed minimum values in ymm1.VEX.256.66.0F EA /rVPMINSW ymm1, ymm2, ymm3/m256BV/VAVX2Compare packed signed word integers in ymm3/m256 and ymm2 and return packed minimum values in ymm1.EVEX.128.66.0F38.WIG 38 /rVPMINSB xmm1{k1}{z}, xmm2, xmm3/m128CV/VAVX512VLAVX512BWCompare packed signed byte integers in xmm2 and xmm3/m128 and store packed minimum values in xmm1 under writemask k1.EVEX.256.66.0F38.WIG 38 /rVPMINSB ymm1{k1}{z}, ymm2, ymm3/m256CV/VAVX512VLAVX512BWCompare packed signed byte integers in ymm2 and ymm3/m256 and store packed minimum values in ymm1 under writemask k1.EVEX.512.66.0F38.WIG 38 /rVPMINSB zmm1{k1}{z}, zmm2, zmm3/m512CV/VAVX512BWCompare packed signed byte integers in zmm2 and zmm3/m512 and store packed minimum values in zmm1 under writemask k1.EVEX.128.66.0F.WIG EA /rVPMINSW xmm1{k1}{z}, xmm2, xmm3/m128CV/VAVX512VLAVX512BWCompare packed signed word integers in xmm2 and xmm3/m128 and store packed minimum values in xmm1 under writemask k1.EVEX.256.66.0F.WIG EA /rVPMINSW ymm1{k1}{z}, ymm2, ymm3/m256CV/VAVX512VLAVX512BWCompare packed signed word integers in ymm2 and ymm3/m256 and store packed minimum values in ymm1 under writemask k1.EVEX.512.66.0F.WIG EA /rVPMINSW zmm1{k1}{z}, zmm2, zmm3/m512CV/VAVX512BWCompare packed signed word integers in zmm2 and zmm3/m512 and store packed minimum values in zmm1 under writemask k1.NOTES:1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACFull MemModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlDescriptionPerforms a SIMD compare of the packed signed byte, word, or dword integers in the second source operand and the first source operand and returns the minimum value for each pair of integers to the destination operand. Legacy SSE version PMINSW: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand can be an MMX technology register.128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding destination register remain unchanged.VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding destination register are zeroed.VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The first source and destination operands are YMM registers.EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is conditionally updated based on writemask k1.OperationPMINSW (64-bit operands)IF DEST[15:0] < SRC[15:0] THENDEST[15:0] := DEST[15:0];ELSEDEST[15:0] := SRC[15:0]; FI;(* Repeat operation for 2nd and 3rd words in source and destination operands *)IF DEST[63:48] < SRC[63:48] THENDEST[63:48] := DEST[63:48];ELSEDEST[63:48] := SRC[63:48]; FI;PMINSB (128-bit Legacy SSE version)IF DEST[7:0] < SRC[7:0] THENDEST[7:0] := DEST[7:0];ELSEDEST[15:0] := SRC[7:0]; FI;(* Repeat operation for 2nd through 15th bytes in source and destination operands *)IF DEST[127:120] < SRC[127:120] THENDEST[127:120] := DEST[127:120];ELSEDEST[127:120] := SRC[127:120]; FI;DEST[MAXVL-1:128] (Unmodified)VPMINSB (VEX.128 encoded version)IF SRC1[7:0] < SRC2[7:0] THENDEST[7:0] := SRC1[7:0];ELSEDEST[7:0] := SRC2[7:0]; FI;(* Repeat operation for 2nd through 15th bytes in source and destination operands *)IF SRC1[127:120] < SRC2[127:120] THENDEST[127:120] := SRC1[127:120];ELSEDEST[127:120] := SRC2[127:120]; FI;DEST[MAXVL-1:128] := 0

image/svg+xmlVPMINSB (VEX.256 encoded version)IF SRC1[7:0] < SRC2[7:0] THENDEST[7:0] := SRC1[7:0];ELSEDEST[15:0] := SRC2[7:0]; FI;(* Repeat operation for 2nd through 31st bytes in source and destination operands *)IF SRC1[255:248] < SRC2[255:248] THENDEST[255:248] := SRC1[255:248];ELSEDEST[255:248] := SRC2[255:248]; FI;DEST[MAXVL-1:256] := 0VPMINSB (EVEX encoded versions)(KL, VL) = (16, 128), (32, 256), (64, 512)FOR j := 0 TO KL-1i := j * 8IF k1[j] OR *no writemask* THENIF SRC1[i+7:i] < SRC2[i+7:i] THEN DEST[i+7:i] := SRC1[i+7:i];ELSE DEST[i+7:i] := SRC2[i+7:i]; FI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+7:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+7:i] := 0FIFI;ENDFOR;DEST[MAXVL-1:VL] := 0PMINSW (128-bit Legacy SSE version)IF DEST[15:0] < SRC[15:0] THENDEST[15:0] := DEST[15:0];ELSEDEST[15:0] := SRC[15:0]; FI;(* Repeat operation for 2nd through 7th words in source and destination operands *)IF DEST[127:112] < SRC[127:112] THENDEST[127:112] := DEST[127:112];ELSEDEST[127:112] := SRC[127:112]; FI;DEST[MAXVL-1:128] (Unmodified)VPMINSW (VEX.128 encoded version)IF SRC1[15:0] < SRC2[15:0] THENDEST[15:0] := SRC1[15:0];ELSEDEST[15:0] := SRC2[15:0]; FI;(* Repeat operation for 2nd through 7th words in source and destination operands *)IF SRC1[127:112] < SRC2[127:112] THENDEST[127:112] := SRC1[127:112];ELSEDEST[127:112] := SRC2[127:112]; FI;DEST[MAXVL-1:128] := 0

image/svg+xmlVPMINSW (VEX.256 encoded version)IF SRC1[15:0] < SRC2[15:0] THENDEST[15:0] := SRC1[15:0];ELSEDEST[15:0] := SRC2[15:0]; FI;(* Repeat operation for 2nd through 15th words in source and destination operands *)IF SRC1[255:240] < SRC2[255:240] THENDEST[255:240] := SRC1[255:240];ELSEDEST[255:240] := SRC2[255:240]; FI;DEST[MAXVL-1:256] := 0VPMINSW (EVEX encoded versions)(KL, VL) = (8, 128), (16, 256), (32, 512)FOR j := 0 TO KL-1i := j * 16IF k1[j] OR *no writemask* THENIF SRC1[i+15:i] < SRC2[i+15:i] THEN DEST[i+15:i] := SRC1[i+15:i];ELSE DEST[i+15:i] := SRC2[i+15:i]; FI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+15:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+15:i] := 0FIFI;ENDFOR;DEST[MAXVL-1:VL] := 0Intel C/C++ Compiler Intrinsic EquivalentVPMINSB __m512i _mm512_min_epi8( __m512i a, __m512i b);VPMINSB __m512i _mm512_mask_min_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);VPMINSB __m512i _mm512_maskz_min_epi8( __mmask64 k, __m512i a, __m512i b);VPMINSW __m512i _mm512_min_epi16( __m512i a, __m512i b);VPMINSW __m512i _mm512_mask_min_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);VPMINSW __m512i _mm512_maskz_min_epi16( __mmask32 k, __m512i a, __m512i b);VPMINSB __m256i _mm256_mask_min_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);VPMINSB __m256i _mm256_maskz_min_epi8( __mmask32 k, __m256i a, __m256i b);VPMINSW __m256i _mm256_mask_min_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);VPMINSW __m256i _mm256_maskz_min_epi16( __mmask16 k, __m256i a, __m256i b);VPMINSB __m128i _mm_mask_min_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);VPMINSB __m128i _mm_maskz_min_epi8( __mmask16 k, __m128i a, __m128i b);VPMINSW __m128i _mm_mask_min_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);VPMINSW __m128i _mm_maskz_min_epi16( __mmask8 k, __m128i a, __m128i b);(V)PMINSB __m128i _mm_min_epi8 ( __m128i a, __m128i b);(V)PMINSW __m128i _mm_min_epi16 ( __m128i a, __m128i b)VPMINSB __m256i _mm256_min_epi8 ( __m256i a, __m256i b);VPMINSW __m256i _mm256_min_epi16 ( __m256i a, __m256i b)PMINSW:__m64 _mm_min_pi16 (__m64 a, __m64 b)

image/svg+xmlSIMD Floating-Point ExceptionsNoneOther ExceptionsNon-EVEX-encoded instruction, see Table2-21, “Type 4 Class Exception Conditions”.EVEX-encoded instruction, see Exceptions Type E4.nb in Table2-49, “Type E4 Class Exception Conditions”.Additionally:#MF(64-bit operations only) If there is a pending x87 FPU exception.

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