PMADDUBSW — Multiply and Add Packed Signed and Unsigned BytesInstruction Operand EncodingDescription (V)PMADDUBSW multiplies vertically each unsigned byte of the destination operand (first operand) with the corre-sponding signed byte of the source operand (second operand), producing intermediate signed 16-bit integers. Each adjacent pair of signed words is added and the saturated result is packed to the destination operand. For example, the lowest-order bytes (bits 7-0) in the source and destination operands are multiplied and the intermediate signed word result is added with the corresponding intermediate result from the 2nd lowest-order bytes (bits 15-8) of the operands; the sign-saturated result is stored in the lowest word of the destination register (15-0). The same oper-ation is performed on the other pairs of adjacent bytes. Both operands can be MMX register or XMM registers. When the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. In 64-bit mode and not encoded with VEX/EVEX, use the REX prefix to access XMM8-XMM15. Opcode/InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F 38 04 /r1PMADDUBSW mm1, mm2/m64AV/VSSSE3Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to mm1. 66 0F 38 04 /r PMADDUBSW xmm1, xmm2/m128 AV/VSSSE3Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to xmm1.VEX.128.66.0F38.WIG 04 /rVPMADDUBSW xmm1, xmm2, xmm3/m128BV/VAVXMultiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to xmm1.VEX.256.66.0F38.WIG 04 /rVPMADDUBSW ymm1, ymm2, ymm3/m256BV/VAVX2Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to ymm1.EVEX.128.66.0F38.WIG 04 /rVPMADDUBSW xmm1 {k1}{z}, xmm2, xmm3/m128CV/VAVX512VLAVX512BWMultiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to xmm1 under writemask k1.EVEX.256.66.0F38.WIG 04 /rVPMADDUBSW ymm1 {k1}{z}, ymm2, ymm3/m256CV/VAVX512VLAVX512BWMultiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to ymm1 under writemask k1.EVEX.512.66.0F38.WIG 04 /rVPMADDUBSW zmm1 {k1}{z}, zmm2, zmm3/m512CV/VAVX512BWMultiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to zmm1 under writemask k1.NOTES:1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACFull MemModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA
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