image/svg+xmlPINSRB/PINSRD/PINSRQ — Insert Byte/Dword/QwordInstruction Operand EncodingDescriptionCopies a byte/dword/qword from the source operand (second operand) and inserts it in the destination operand (first operand) at the location specified with the count operand (third operand). (The other elements in the desti-nation register are left untouched.) The source operand can be a general-purpose register or a memory location. (When the source operand is a general-purpose register, PINSRB copies the low byte of the register.) The destina-tion operand is an XMM register. The count operand is an 8-bit immediate. When specifying a qword[dword, byte] location in an XMM register, the [2, 4] least-significant bit(s) of the count operand specify the location.Opcode/InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F 3A 20 /r ibPINSRB xmm1, r32/m8, imm8AV/VSSE4_1Insert a byte integer value from r32/m8 into xmm1 at the destination element in xmm1 specified by imm8.66 0F 3A 22 /r ibPINSRD xmm1, r/m32, imm8AV/VSSE4_1Insert a dword integer value from r/m32 into the xmm1 at the destination element specified by imm8.66 REX.W 0F 3A 22 /r ibPINSRQ xmm1, r/m64, imm8AV/N. E.SSE4_1Insert a qword integer value from r/m64 into the xmm1 at the destination element specified by imm8.VEX.128.66.0F3A.W0 20 /r ibVPINSRB xmm1, xmm2, r32/m8, imm8BV1/VNOTES:1. In 64-bit mode, VEX.W1 is ignored for VPINSRB (similar to legacy REX.W=1 prefix with PINSRB).AVXMerge a byte integer value from r32/m8 and rest from xmm2 into xmm1 at the byte offset in imm8.VEX.128.66.0F3A.W0 22 /r ibVPINSRD xmm1, xmm2, r/m32, imm8BV/VAVXInsert a dword integer value from r32/m32 and rest from xmm2 into xmm1 at the dword offset in imm8.VEX.128.66.0F3A.W1 22 /r ibVPINSRQ xmm1, xmm2, r/m64, imm8BV/I22. VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.AVXInsert a qword integer value from r64/m64 and rest from xmm2 into xmm1 at the qword offset in imm8.EVEX.128.66.0F3A.WIG 20 /r ibVPINSRB xmm1, xmm2, r32/m8, imm8CV/VAVX512BWMerge a byte integer value from r32/m8 and rest from xmm2 into xmm1 at the byte offset in imm8.EVEX.128.66.0F3A.W0 22 /r ibVPINSRD xmm1, xmm2, r32/m32, imm8CV/VAVX512DQInsert a dword integer value from r32/m32 and rest from xmm2 into xmm1 at the dword offset in imm8.EVEX.128.66.0F3A.W1 22 /r ibVPINSRQ xmm1, xmm2, r64/m64, imm8CV/N.E.2AVX512DQInsert a qword integer value from r64/m64 and rest from xmm2 into xmm1 at the qword offset in imm8.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)imm8NABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)imm8CTuple1 ScalarModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)Imm8

image/svg+xmlIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15, R8-15). Use of REX.W permits the use of 64 bit general purpose regis-ters.128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.VEX.128 encoded version: Bits (MAXVL-1:128) of the destination register are zeroed. VEX.L must be 0, otherwise the instruction will #UD. Attempt to execute VPINSRQ in non-64-bit mode will cause #UD.EVEX.128 encoded version: Bits (MAXVL-1:128) of the destination register are zeroed. EVEX.L’L must be 0, other-wise the instruction will #UD. OperationCASE OFPINSRB:SEL := COUNT[3:0];MASK := (0FFH << (SEL * 8)); TEMP := (((SRC[7:0] << (SEL *8)) AND MASK);PINSRD:SEL := COUNT[1:0];MASK := (0FFFFFFFFH << (SEL * 32)); TEMP := (((SRC << (SEL *32)) AND MASK);PINSRQ:SEL := COUNT[0]MASK := (0FFFFFFFFFFFFFFFFH << (SEL * 64)); TEMP := (((SRC << (SEL *64)) AND MASK);ESAC;DEST := ((DEST AND NOT MASK) OR TEMP); VPINSRB (VEX/EVEX encoded version)SEL := imm8[3:0]DEST[127:0] := write_b_element(SEL, SRC2, SRC1)DEST[MAXVL-1:128] := 0VPINSRD (VEX/EVEX encoded version)SEL := imm8[1:0]DEST[127:0] := write_d_element(SEL, SRC2, SRC1)DEST[MAXVL-1:128] := 0VPINSRQ (VEX/EVEX encoded version)SEL := imm8[0]DEST[127:0] := write_q_element(SEL, SRC2, SRC1)DEST[MAXVL-1:128] := 0Intel C/C++ Compiler Intrinsic EquivalentPINSRB: __m128i _mm_insert_epi8 (__m128i s1, int s2, const int ndx);PINSRD: __m128i _mm_insert_epi32 (__m128i s2, int s, const int ndx);PINSRQ: __m128i _mm_insert_epi64(__m128i s2, __int64 s, const int ndx);Flags AffectedNone.SIMD Floating-Point ExceptionsNone.

image/svg+xmlOther ExceptionsEVEX-encoded instruction, see Table2-22, “Type 5 Class Exception Conditions”. EVEX-encoded instruction, see Table2-57, “Type E9NF Class Exception Conditions”.Additionally:#UD If VEX.L = 1 or EVEX.L’L > 0.

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