image/svg+xmlPHMINPOSUW — Packed Horizontal Word MinimumInstruction Operand EncodingDescriptionDetermine the minimum unsigned word value in the source operand (second operand) and place the unsigned word in the low word (bits 0-15) of the destination operand (first operand). The word index of the minimum value is stored in bits 16-18 of the destination operand. The remaining upper bits of the destination are set to zero. 128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding XMM destination register remain unchanged.VEX.128 encoded version: Bits (MAXVL-1:128) of the destination XMM register are zeroed. VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the instruction will #UD.OperationPHMINPOSUW (128-bit Legacy SSE version)INDEX := 0;MIN := SRC[15:0]IF (SRC[31:16] < MIN) THEN INDEX := 1; MIN := SRC[31:16]; FI;IF (SRC[47:32] < MIN) THEN INDEX := 2; MIN := SRC[47:32]; FI;* Repeat operation for words 3 through 6IF (SRC[127:112] < MIN) THEN INDEX := 7; MIN := SRC[127:112]; FI;DEST[15:0] := MIN;DEST[18:16] := INDEX;DEST[127:19] := 0000000000000000000000000000H;Opcode/InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F 38 41 /rPHMINPOSUW xmm1, xmm2/m128RMV/VSSE4_1Find the minimum unsigned word in xmm2/m128 and place its value in the low word of xmm1 and its index in the second-lowest word of xmm1.VEX.128.66.0F38.WIG 41 /rVPHMINPOSUW xmm1, xmm2/m128RMV/VAVXFind the minimum unsigned word in xmm2/m128 and place its value in the low word of xmm1 and its index in the second-lowest word of xmm1.Op/EnOperand 1Operand 2Operand 3Operand 4RMModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlVPHMINPOSUW (VEX.128 encoded version)INDEX := 0MIN := SRC[15:0]IF (SRC[31:16] < MIN) THEN INDEX := 1; MIN := SRC[31:16]IF (SRC[47:32] < MIN) THEN INDEX := 2; MIN := SRC[47:32]* Repeat operation for words 3 through 6IF (SRC[127:112] < MIN) THEN INDEX := 7; MIN := SRC[127:112]DEST[15:0] := MINDEST[18:16] := INDEXDEST[127:19] := 0000000000000000000000000000HDEST[MAXVL-1:128] := 0Intel C/C++ Compiler Intrinsic EquivalentPHMINPOSUW:__m128i _mm_minpos_epu16( __m128i packed_words);Flags AffectedNone.SIMD Floating-Point ExceptionsNone.Other ExceptionsSee Table2-21, “Type 4 Class Exception Conditions”; additionally:#UDIf VEX.L = 1.If VEX.vvvv ≠ 1111B.

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