image/svg+xmlPEXT — Parallel Bits ExtractInstruction Operand EncodingDescription PEXT uses a mask in the second source operand (the third operand) to transfer either contiguous or non-contig-uous bits in the first source operand (the second operand) to contiguous low order bit positions in the destination (the first operand). For each bit set in the MASK, PEXT extracts the corresponding bits from the first source operand and writes them into contiguous lower bits of destination operand. The remaining upper bits of destination are zeroed.Figure 4-9. PEXT ExampleThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.Opcode/InstructionOp/ En64/32-bit ModeCPUID Feature FlagDescriptionVEX.LZ.F3.0F38.W0 F5 /rPEXT r32a, r32b, r/m32RVMV/VBMI2Parallel extract of bits from r32b using mask in r/m32, result is writ-ten to r32a.VEX.LZ.F3.0F38.W1 F5 /rPEXT r64a, r64b, r/m64RVMV/N.E.BMI2Parallel extract of bits from r64b using mask in r/m64, result is writ-ten to r64a.Op/EnOperand 1Operand 2Operand 3Operand 4RVMModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NADESTSRC1SRC2(mask)S31S30S29S28S27S7S6S5S3S4S2S1S0001010101000S2S5S70000000000S28bit 0bit 31

image/svg+xmlOperationTEMP := SRC1;MASK := SRC2;DEST := 0 ;m := 0, k := 0;DOWHILE m < OperandSizeIF MASK[ m] = 1 THENDEST[ k] := TEMP[ m]; k := k+ 1;FIm := m+ 1;ODFlags AffectedNone.Intel C/C++ Compiler Intrinsic EquivalentPEXT:unsigned __int32 _pext_u32(unsigned __int32 src, unsigned __int32 mask);PEXT:unsigned __int64 _pext_u64(unsigned __int64 src, unsigned __int32 mask);SIMD Floating-Point ExceptionsNoneOther ExceptionsSee Table2-29, “Type 13 Class Exception Conditions”.

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