image/svg+xmlPDEP — Parallel Bits DepositInstruction Operand EncodingDescription PDEP uses a mask in the second source operand (the third operand) to transfer/scatter contiguous low order bits in the first source operand (the second operand) into the destination (the first operand). PDEP takes the low bits from the first source operand and deposit them in the destination operand at the corresponding bit locations that are set in the second source operand (mask). All other bits (bits not set in mask) in destination are set to zero.Figure 4-8. PDEP ExampleThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.OperationTEMP := SRC1;MASK := SRC2;DEST := 0 ;m := 0, k := 0;DOWHILE m < OperandSizeIF MASK[ m] = 1 THENDEST[ m] := TEMP[ k]; k := k+ 1;FIm := m+ 1;ODOpcode/InstructionOp/ En64/32-bit ModeCPUID Feature FlagDescriptionVEX.LZ.F2.0F38.W0 F5 /rPDEP r32a, r32b, r/m32RVMV/VBMI2Parallel deposit of bits from r32b using mask in r/m32, result is writ-ten to r32a.VEX.LZ.F2.0F38.W1 F5 /rPDEP r64a, r64b, r/m64RVMV/N.E.BMI2Parallel deposit of bits from r64b using mask in r/m64, result is writ-ten to r64a.Op/EnOperand 1Operand 2Operand 3Operand 4RVMModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NA0010010101000000000000DESTSRC1SRC2(mask)S31S30S29S28S27S7S6S5S3S4S2S1S0S0S1S2S3bit 0bit 31

image/svg+xmlFlags AffectedNone.Intel C/C++ Compiler Intrinsic EquivalentPDEP:unsigned __int32 _pdep_u32(unsigned __int32 src, unsigned __int32 mask);PDEP:unsigned __int64 _pdep_u64(unsigned __int64 src, unsigned __int32 mask);SIMD Floating-Point ExceptionsNoneOther ExceptionsSee Table2-29, “Type 13 Class Exception Conditions”.

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