image/svg+xml PCMPESTRI — Packed Compare Explicit Length Strings, Return Index Instruction Operand Encoding Description The instruction compares and processes data from two string fragments based on the encoded value in the Imm8 Control Byte (see Section 4.1, “Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMP- ISTRM”), and generates an index stored to the count register (ECX). Each string fragment is represented by two values. The first value is an xmm (or possibly m128 for the second operand) which contains the data elements of the string (byte or word data). The second value is stored in an input length register. The input length register is EAX/RAX (for xmm1) or EDX/RDX (for xmm2/m128). The length repre- sents the number of bytes/words which are valid for the respective xmm/m128 data. The length of each input is interpreted as being the absolute-value of the value in the length register. The absolute- value computation saturates to 16 (for bytes) and 8 (for words), based on the value of imm8[bit3] when the value in the length register is greater than 16 (8) or less than -16 (-8). The comparison and aggregation operations are performed according to the encoded value of Imm8 bit fields (see Section 4.1). The index of the first (or last, according to imm8[6]) set bit of IntRes2 (see Section 4.1.4) is returned in ECX. If no bits are set in IntRes2, ECX is set to 16 (8). Note that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant informa- tion: CFlag – Reset if IntRes2 is equal to zero, set otherwise ZFlag – Set if absolute-value of EDX is < 16 (8), reset otherwise SFlag – Set if absolute-value of EAX is < 16 (8), reset otherwise OFlag – IntRes2[0] AFlag – Reset PFlag – Reset Effective Operand Size Intel C/C++ Compiler Intrinsic Equivalent For Returning Index int _mm_cmpestri (__m128i a, int la, __m128i b, int lb, const int mode); Opcode/ Instruction Op/ En 64/32 bit Mode Support CPUID Feature Flag Description 66 0F 3A 61 /r imm8 PCMPESTRI xmm1, xmm2/m128, imm8 RMIV/VSSE4_2Perform a packed comparison of string data with explicit lengths, generating an index, and storing the result in ECX. VEX.128.66.0F3A 61 /r ib VPCMPESTRI xmm1, xmm2/m128, imm8 RMIV/VAVXPerform a packed comparison of string data with explicit lengths, generating an index, and storing the result in ECX. Op/EnOperand 1Operand 2Operand 3Operand 4 RMIModRM:reg (r)ModRM:r/m (r)imm8NA Operating mode/sizeOperand 1Operand 2Length 1Length 2Result 16 bitxmmxmm/m128EAXEDXECX 32 bitxmmxmm/m128EAXEDXECX 64 bitxmmxmm/m128EAXEDXECX 64 bit + REX.Wxmmxmm/m128RAXRDXECX image/svg+xml Intel C/C++ Compiler Intrinsics For Reading EFlag Results int _mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode); int _mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode); int _mm_cmpestro (__m128i a, int la, __m128i b, int lb, const int mode); int _mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode); int _mm_cmpestrz (__m128i a, int la, __m128i b, int lb, const int mode); SIMD Floating-Point Exceptions None. Other Exceptions See Table2-21, “Type 4 Class Exception Conditions”; additionally, this instruction does not cause #GP if the memory operand is not aligned to 16 Byte boundary, and: #UDIf VEX.L = 1. If VEX.vvvv ≠ 1111B. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .