image/svg+xmlPCLMULQDQ—Carry-Less Multiplication QuadwordInstruction Operand EncodingDescriptionPerforms a carry-less multiplication of two quadwords, selected from the first source and second source operand according to the value of the immediate byte. Bits 4 and 0 are used to select which 64-bit half of each operand to use according to Table4-13, other bits of the immediate byte are ignored. The EVEX encoded form of this instruction does not support memory fault suppression.Opcode/InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F 3A 44 /r ibPCLMULQDQ xmm1, xmm2/m128, imm8AV/VPCLMULQDQCarry-less multiplication of one quadword of xmm1 by one quadword of xmm2/m128, stores the 128-bit result in xmm1. The imme-diate is used to determine which quadwords of xmm1 and xmm2/m128 should be used.VEX.128.66.0F3A.WIG 44 /r ibVPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8BV/VPCLMULQDQ AVXCarry-less multiplication of one quadword of xmm2 by one quadword of xmm3/m128, stores the 128-bit result in xmm1. The imme-diate is used to determine which quadwords of xmm2 and xmm3/m128 should be used.VEX.256.66.0F3A.WIG 44 /r /ib VPCLMULQDQ ymm1, ymm2, ymm3/m256, imm8BV/VVPCLMULQDQCarry-less multiplication of one quadword of ymm2 by one quadword of ymm3/m256, stores the 128-bit result in ymm1. The imme-diate is used to determine which quadwords of ymm2 and ymm3/m256 should be used.EVEX.128.66.0F3A.WIG 44 /r /ibVPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8CV/VVPCLMULQDQAVX512VLCarry-less multiplication of one quadword of xmm2 by one quadword of xmm3/m128, stores the 128-bit result in xmm1. The imme-diate is used to determine which quadwords of xmm2 and xmm3/m128 should be used.EVEX.256.66.0F3A.WIG 44 /r /ibVPCLMULQDQ ymm1, ymm2, ymm3/m256, imm8CV/VVPCLMULQDQAVX512VLCarry-less multiplication of one quadword of ymm2 by one quadword of ymm3/m256, stores the 128-bit result in ymm1. The imme-diate is used to determine which quadwords of ymm2 and ymm3/m256 should be used.EVEX.512.66.0F3A.WIG 44 /r /ibVPCLMULQDQ zmm1, zmm2, zmm3/m512, imm8CV/VVPCLMULQDQAVX512FCarry-less multiplication of one quadword of zmm2 by one quadword of zmm3/m512, stores the 128-bit result in zmm1. The imme-diate is used to determine which quadwords of zmm2 and zmm3/m512 should be used.Op/EnTupleOperand 1Operand2Operand3Operand4ANAModRM:reg (r, w)ModRM:r/m (r)imm8NABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)imm8CFull MemModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)imm8 (r)

image/svg+xmlThe first source operand and the destination operand are the same and must be a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location. Bits (VL_MAX-1:128) of the corresponding YMM destination register remain unchanged.Compilers and assemblers may implement the following pseudo-op syntax to simplify programming and emit the required encoding for imm8.Operationdefine PCLMUL128(X,Y): // helper functionFOR i := 0 to 63:TMP [ i ] := X[ 0 ] and Y[ i ]FOR j := 1 to i:TMP [ i ] := TMP [ i ] xor (X[ j ] and Y[ i - j ])DEST[ i ] := TMP[ i ]FOR i := 64 to 126:TMP [ i ] := 0FOR j := i - 63 to 63:TMP [ i ] := TMP [ i ] xor (X[ j ] and Y[ i - j ])DEST[ i ] := TMP[ i ]DEST[127] := 0;RETURN DEST // 128b vectorTable 4-13. PCLMULQDQ Quadword Selection of Immediate ByteImm[4]Imm[0]PCLMULQDQ Operation00CL_MUL( SRC21[63:0], SRC1[63:0] )NOTES:1. SRC2 denotes the second source operand, which can be a register or memory; SRC1 denotes the first source and destination oper-and.01CL_MUL( SRC2[63:0], SRC1[127:64] )10CL_MUL( SRC2[127:64], SRC1[63:0] )11CL_MUL( SRC2[127:64], SRC1[127:64] )Table 4-14. Pseudo-Op and PCLMULQDQ ImplementationPseudo-OpImm8 EncodingPCLMULLQLQDQ xmm1, xmm20000_0000BPCLMULHQLQDQ xmm1, xmm20000_0001BPCLMULLQHQDQ xmm1, xmm20001_0000BPCLMULHQHQDQ xmm1, xmm20001_0001B

image/svg+xmlPCLMULQDQ (SSE version)IF Imm8[0] = 0:TEMP1 := SRC1.qword[0]ELSE:TEMP1 := SRC1.qword[1]IF Imm8[4] = 0:TEMP2 := SRC2.qword[0]ELSE:TEMP2 := SRC2.qword[1]DEST[127:0] := PCLMUL128(TEMP1, TEMP2)DEST[MAXVL-1:128] (Unmodified)VPCLMULQDQ (128b and 256b VEX encoded versions)(KL,VL) = (1,128), (2,256)FOR i= 0 to KL-1:IF Imm8[0] = 0:TEMP1 := SRC1.xmm[i].qword[0]ELSE:TEMP1 := SRC1.xmm[i].qword[1]IF Imm8[4] = 0:TEMP2 := SRC2.xmm[i].qword[0]ELSE:TEMP2 := SRC2.xmm[i].qword[1]DEST.xmm[i] := PCLMUL128(TEMP1, TEMP2)DEST[MAXVL-1:VL] := 0VPCLMULQDQ (EVEX encoded version)(KL,VL) = (1,128), (2,256), (4,512)FOR i = 0 to KL-1:IF Imm8[0] = 0:TEMP1 := SRC1.xmm[i].qword[0]ELSE:TEMP1 := SRC1.xmm[i].qword[1]IF Imm8[4] = 0:TEMP2 := SRC2.xmm[i].qword[0]ELSE:TEMP2 := SRC2.xmm[i].qword[1]DEST.xmm[i] := PCLMUL128(TEMP1, TEMP2)DEST[MAXVL-1:VL] := 0Intel C/C++ Compiler Intrinsic Equivalent(V)PCLMULQDQ__m128i _mm_clmulepi64_si128 (__m128i, __m128i, const int)VPCLMULQDQ __m256i _mm256_clmulepi64_epi128(__m256i, __m256i, const int);VPCLMULQDQ __m512i _mm512_clmulepi64_epi128(__m512i, __m512i, const int);SIMD Floating-Point ExceptionsNone.

image/svg+xmlOther ExceptionsSee Table2-21, “Type 4 Class Exception Conditions”, additionally:#UDIf VEX.L = 1.EVEX-encoded: See Table2-50, “Type E4NF Class Exception Conditions”.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.