image/svg+xmlPANDN—Logical AND NOTInstruction Operand EncodingDescriptionPerforms a bitwise logical NOT operation on the first source operand, then performs bitwise AND with second source operand and stores the result in the destination operand. Each bit of the result is set to 1 if the corre-sponding bit in the first operand is 0 and the corresponding bit in the second operand is 1, otherwise it is set to 0.In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).Opcode/InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F DF /r1PANDN mm, mm/m64AV/VMMXBitwise AND NOT of mm/m64 and mm.66 0F DF /rPANDN xmm1, xmm2/m128AV/VSSE2Bitwise AND NOT of xmm2/m128 and xmm1.VEX.128.66.0F.WIG DF /rVPANDN xmm1, xmm2, xmm3/m128BV/VAVXBitwise AND NOT of xmm3/m128 and xmm2.VEX.256.66.0F.WIG DF /rVPANDN ymm1, ymm2, ymm3/m256BV/VAVX2Bitwise AND NOT of ymm2, and ymm3/m256 and store result in ymm1.EVEX.128.66.0F.W0 DF /rVPANDND xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst CV/VAVX512VLAVX512FBitwise AND NOT of packed doubleword integers in xmm2 and xmm3/m128/m32bcst and store result in xmm1 using writemask k1. EVEX.256.66.0F.W0 DF /rVPANDND ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst CV/VAVX512VLAVX512FBitwise AND NOT of packed doubleword integers in ymm2 and ymm3/m256/m32bcst and store result in ymm1 using writemask k1. EVEX.512.66.0F.W0 DF /rVPANDND zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst CV/VAVX512FBitwise AND NOT of packed doubleword integers in zmm2 and zmm3/m512/m32bcst and store result in zmm1 using writemask k1. EVEX.128.66.0F.W1 DF /rVPANDNQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst CV/VAVX512VLAVX512FBitwise AND NOT of packed quadword integers in xmm2 and xmm3/m128/m64bcst and store result in xmm1 using writemask k1. EVEX.256.66.0F.W1 DF /rVPANDNQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst CV/VAVX512VLAVX512FBitwise AND NOT of packed quadword integers in ymm2 and ymm3/m256/m64bcst and store result in ymm1 using writemask k1. EVEX.512.66.0F.W1 DF /rVPANDNQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst CV/VAVX512FBitwise AND NOT of packed quadword integers in zmm2 and zmm3/m512/m64bcst and store result in zmm1 using writemask k1. NOTES:1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACFullModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlLegacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand can be an MMX technology register.128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified.EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1 at 32/64-bit granularity.VEX.256 encoded versions: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding ZMM register destination are zeroed.VEX.128 encoded versions: The first source operand is an XMM register. The second source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.OperationPANDN (64-bit operand)DEST := NOT(DEST) AND SRCPANDN (128-bit Legacy SSE version)DEST := NOT(DEST) AND SRCDEST[MAXVL-1:128] (Unmodified)VPANDN (VEX.128 encoded version)DEST := NOT(SRC1) AND SRC2DEST[MAXVL-1:128] := 0VPANDN (VEX.256 encoded instruction)DEST[255:0] := ((NOT SRC1[255:0]) AND SRC2[255:0])DEST[MAXVL-1:256] := 0VPANDND (EVEX encoded versions) (KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no writemask*THEN IF (EVEX.b = 1) AND (SRC2 *is memory*)THEN DEST[i+31:i] := ((NOT SRC1[i+31:i]) AND SRC2[31:0])ELSE DEST[i+31:i] := ((NOT SRC1[i+31:i]) AND SRC2[i+31:i])FI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0

image/svg+xmlVPANDNQ (EVEX encoded versions) (KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64IF k1[j] OR *no writemask*THEN IF (EVEX.b = 1) AND (SRC2 *is memory*)THEN DEST[i+63:i] := ((NOT SRC1[i+63:i]) AND SRC2[63:0])ELSE DEST[i+63:i] := ((NOT SRC1[i+63:i]) AND SRC2[i+63:i])FI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+63:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+63:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0Intel C/C++ Compiler Intrinsic EquivalentsVPANDND __m512i _mm512_andnot_epi32( __m512i a, __m512i b);VPANDND __m512i _mm512_mask_andnot_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);VPANDND __m512i _mm512_maskz_andnot_epi32( __mmask16 k, __m512i a, __m512i b);VPANDND __m256i _mm256_mask_andnot_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);VPANDND __m256i _mm256_maskz_andnot_epi32( __mmask8 k, __m256i a, __m256i b);VPANDND __m128i _mm_mask_andnot_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);VPANDND __m128i _mm_maskz_andnot_epi32( __mmask8 k, __m128i a, __m128i b);VPANDNQ __m512i _mm512_andnot_epi64( __m512i a, __m512i b);VPANDNQ __m512i _mm512_mask_andnot_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);VPANDNQ __m512i _mm512_maskz_andnot_epi64( __mmask8 k, __m512i a, __m512i b);VPANDNQ __m256i _mm256_mask_andnot_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);VPANDNQ __m256i _mm256_maskz_andnot_epi64( __mmask8 k, __m256i a, __m256i b);VPANDNQ __m128i _mm_mask_andnot_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);VPANDNQ __m128i _mm_maskz_andnot_epi64( __mmask8 k, __m128i a, __m128i b);PANDN: __m64 _mm_andnot_si64 (__m64 m1, __m64 m2)(V)PANDN:__m128i _mm_andnot_si128 ( __m128i a, __m128i b)VPANDN:__m256i _mm256_andnot_si256 ( __m256i a, __m256i b)Flags AffectedNone.Numeric ExceptionsNone.Other ExceptionsNon-EVEX-encoded instruction, see Table2-21, “Type 4 Class Exception Conditions”.EVEX-encoded instruction, see Table2-49, “Type E4 Class Exception Conditions”.

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