PALIGNR — Packed Align Right Instruction Operand EncodingDescription (V)PALIGNR concatenates the destination operand (the first operand) and the source operand (the second operand) into an intermediate composite, shifts the composite at byte granularity to the right by a constant imme-diate, and extracts the right-aligned result into the destination. The first and the second operands can be an MMX, Opcode/InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F 3A 0F /r ib1PALIGNR mm1, mm2/m64, imm8AV/VSSSE3Concatenate destination and source operands, extract byte-aligned result shifted to the right by constant value in imm8 into mm1. 66 0F 3A 0F /r ibPALIGNR xmm1, xmm2/m128, imm8AV/VSSSE3Concatenate destination and source operands, extract byte-aligned result shifted to the right by constant value in imm8 into xmm1.VEX.128.66.0F3A.WIG 0F /r ibVPALIGNR xmm1, xmm2, xmm3/m128, imm8BV/VAVXConcatenate xmm2 and xmm3/m128, extract byte aligned result shifted to the right by constant value in imm8 and result is stored in xmm1.VEX.256.66.0F3A.WIG 0F /r ibVPALIGNR ymm1, ymm2, ymm3/m256, imm8BV/VAVX2Concatenate pairs of 16 bytes in ymm2 and ymm3/m256 into 32-byte intermediate result, extract byte-aligned, 16-byte result shifted to the right by constant values in imm8 from each intermediate result, and two 16-byte results are stored in ymm1.EVEX.128.66.0F3A.WIG 0F /r ibVPALIGNR xmm1 {k1}{z}, xmm2, xmm3/m128, imm8CV/VAVX512VLAVX512BWConcatenate xmm2 and xmm3/m128 into a 32-byte intermediate result, extract byte aligned result shifted to the right by constant value in imm8 and result is stored in xmm1.EVEX.256.66.0F3A.WIG 0F /r ibVPALIGNR ymm1 {k1}{z}, ymm2, ymm3/m256, imm8CV/VAVX512VLAVX512BWConcatenate pairs of 16 bytes in ymm2 and ymm3/m256 into 32-byte intermediate result, extract byte-aligned, 16-byte result shifted to the right by constant values in imm8 from each intermediate result, and two 16-byte results are stored in ymm1.EVEX.512.66.0F3A.WIG 0F /r ibVPALIGNR zmm1 {k1}{z}, zmm2, zmm3/m512, imm8CV/VAVX512BWConcatenate pairs of 16 bytes in zmm2 and zmm3/m512 into 32-byte intermediate result, extract byte-aligned, 16-byte result shifted to the right by constant values in imm8 from each intermediate result, and four 16-byte results are stored in zmm1.NOTES:1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)imm8NABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)imm8CFull MemModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)imm8
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