image/svg+xmlPABSB/PABSW/PABSD/PABSQ — Packed Absolute Value Opcode/InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F 38 1C /r1PABSB mm1, mm2/m64 AV/VSSSE3Compute the absolute value of bytes in mm2/m64 and store UNSIGNED result in mm1.66 0F 38 1C /r PABSB xmm1, xmm2/m128 AV/VSSSE3Compute the absolute value of bytes in xmm2/m128 and store UNSIGNED result in xmm1. NP 0F 38 1D /r1PABSW mm1, mm2/m64 AV/VSSSE3Compute the absolute value of 16-bit integers in mm2/m64 and store UNSIGNED result in mm1.66 0F 38 1D /rPABSW xmm1, xmm2/m128AV/VSSSE3Compute the absolute value of 16-bit integers in xmm2/m128 and store UNSIGNED result in xmm1.NP 0F 38 1E /r1 PABSD mm1, mm2/m64 AV/VSSSE3Compute the absolute value of 32-bit integers in mm2/m64 and store UNSIGNED result in mm1. 66 0F 38 1E /r PABSD xmm1, xmm2/m128 AV/VSSSE3Compute the absolute value of 32-bit integers in xmm2/m128 and store UNSIGNED result in xmm1. VEX.128.66.0F38.WIG 1C /rVPABSB xmm1, xmm2/m128AV/VAVXCompute the absolute value of bytes in xmm2/m128 and store UNSIGNED result in xmm1.VEX.128.66.0F38.WIG 1D /rVPABSW xmm1, xmm2/m128AV/VAVXCompute the absolute value of 16- bit integers in xmm2/m128 and store UNSIGNED result in xmm1.VEX.128.66.0F38.WIG 1E /rVPABSD xmm1, xmm2/m128AV/VAVXCompute the absolute value of 32- bit integers in xmm2/m128 and store UNSIGNED result in xmm1.VEX.256.66.0F38.WIG 1C /rVPABSB ymm1, ymm2/m256AV/VAVX2Compute the absolute value of bytes in ymm2/m256 and store UNSIGNED result in ymm1.VEX.256.66.0F38.WIG 1D /rVPABSW ymm1, ymm2/m256AV/VAVX2Compute the absolute value of 16-bit integers in ymm2/m256 and store UNSIGNED result in ymm1.VEX.256.66.0F38.WIG 1E /rVPABSD ymm1, ymm2/m256AV/VAVX2Compute the absolute value of 32-bit integers in ymm2/m256 and store UNSIGNED result in ymm1.EVEX.128.66.0F38.WIG 1C /rVPABSB xmm1 {k1}{z}, xmm2/m128BV/VAVX512VLAVX512BWCompute the absolute value of bytes in xmm2/m128 and store UNSIGNED result in xmm1 using writemask k1.EVEX.256.66.0F38.WIG 1C /rVPABSB ymm1 {k1}{z}, ymm2/m256BV/VAVX512VLAVX512BWCompute the absolute value of bytes in ymm2/m256 and store UNSIGNED result in ymm1 using writemask k1.EVEX.512.66.0F38.WIG 1C /rVPABSB zmm1 {k1}{z}, zmm2/m512BV/VAVX512BWCompute the absolute value of bytes in zmm2/m512 and store UNSIGNED result in zmm1 using writemask k1.EVEX.128.66.0F38.WIG 1D /r VPABSW xmm1 {k1}{z}, xmm2/m128BV/VAVX512VLAVX512BWCompute the absolute value of 16-bit integers in xmm2/m128 and store UNSIGNED result in xmm1 using writemask k1.

image/svg+xmlInstruction Operand EncodingDescription PABSB/W/D computes the absolute value of each data element of the source operand (the second operand) and stores the UNSIGNED results in the destination operand (the first operand). PABSB operates on signed bytes, PABSW operates on signed 16-bit words, and PABSD operates on signed 32-bit integers. EVEX encoded VPABSD/Q: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register updated according to the writemask. EVEX encoded VPABSB/W: The source operand is a ZMM/YMM/XMM register, or a 512/256/128-bit memory loca-tion. The destination operand is a ZMM/YMM/XMM register updated according to the writemask. VEX.256 encoded versions: The source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding register destination are zeroed.VEX.128 encoded versions: The source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding register destination are zeroed.EVEX.256.66.0F38.WIG 1D /r VPABSW ymm1 {k1}{z}, ymm2/m256 BV/VAVX512VLAVX512BWCompute the absolute value of 16-bit integers in ymm2/m256 and store UNSIGNED result in ymm1 using writemask k1.EVEX.512.66.0F38.WIG 1D /r VPABSW zmm1 {k1}{z}, zmm2/m512BV/VAVX512BWCompute the absolute value of 16-bit integers in zmm2/m512 and store UNSIGNED result in zmm1 using writemask k1.EVEX.128.66.0F38.W0 1E /rVPABSD xmm1 {k1}{z}, xmm2/m128/m32bcstCV/VAVX512VLAVX512FCompute the absolute value of 32-bit integers in xmm2/m128/m32bcst and store UNSIGNED result in xmm1 using writemask k1. EVEX.256.66.0F38.W0 1E /rVPABSD ymm1 {k1}{z}, ymm2/m256/m32bcstCV/VAVX512VLAVX512FCompute the absolute value of 32-bit integers in ymm2/m256/m32bcst and store UNSIGNED result in ymm1 using writemask k1. EVEX.512.66.0F38.W0 1E /rVPABSD zmm1 {k1}{z}, zmm2/m512/m32bcst CV/VAVX512FCompute the absolute value of 32-bit integers in zmm2/m512/m32bcst and store UNSIGNED result in zmm1 using writemask k1. EVEX.128.66.0F38.W1 1F /rVPABSQ xmm1 {k1}{z}, xmm2/m128/m64bcstCV/VAVX512VLAVX512FCompute the absolute value of 64-bit integers in xmm2/m128/m64bcst and store UNSIGNED result in xmm1 using writemask k1. EVEX.256.66.0F38.W1 1F /rVPABSQ ymm1 {k1}{z}, ymm2/m256/m64bcstCV/VAVX512VLAVX512FCompute the absolute value of 64-bit integers in ymm2/m256/m64bcst and store UNSIGNED result in ymm1 using writemask k1. EVEX.512.66.0F38.W1 1F /rVPABSQ zmm1 {k1}{z}, zmm2/m512/m64bcst CV/VAVX512FCompute the absolute value of 64-bit integers in zmm2/m512/m64bcst and store UNSIGNED result in zmm1 using writemask k1. NOTES:1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)NANABFull MemModRM:reg (w)ModRM:r/m (r)NANACFullModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xml128-bit Legacy SSE version: The source operand can be an XMM register or an 128-bit memory location. The desti-nation is an XMM register. The upper bits (VL_MAX-1:128) of the corresponding register destination are unmodi-fied.VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.OperationPABSB with 128 bit operands:Unsigned DEST[7:0] := ABS(SRC[7: 0]) Repeat operation for 2nd through 15th bytes Unsigned DEST[127:120] := ABS(SRC[127:120])VPABSB with 128 bit operands:Unsigned DEST[7:0] := ABS(SRC[7: 0]) Repeat operation for 2nd through 15th bytes Unsigned DEST[127:120] := ABS(SRC[127:120])VPABSB with 256 bit operands:Unsigned DEST[7:0] := ABS(SRC[7: 0]) Repeat operation for 2nd through 31st bytes Unsigned DEST[255:248] := ABS(SRC[255:248]) VPABSB (EVEX encoded versions)(KL, VL) = (16, 128), (32, 256), (64, 512)FOR j := 0 TO KL-1i := j * 8IF k1[j] OR *no writemask*THEN Unsigned DEST[i+7:i] := ABS(SRC[i+7:i])ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+7:i] remains unchanged*ELSE *zeroing-masking*; zeroing-maskingDEST[i+7:i] := 0FIFI;ENDFOR;DEST[MAXVL-1:VL] := 0PABSW with 128 bit operands:Unsigned DEST[15:0] := ABS(SRC[15:0]) Repeat operation for 2nd through 7th 16-bit words Unsigned DEST[127:112] := ABS(SRC[127:112]) VPABSW with 128 bit operands:Unsigned DEST[15:0] := ABS(SRC[15:0]) Repeat operation for 2nd through 7th 16-bit words Unsigned DEST[127:112] := ABS(SRC[127:112]) VPABSW with 256 bit operands:Unsigned DEST[15:0] := ABS(SRC[15:0]) Repeat operation for 2nd through 15th 16-bit words Unsigned DEST[255:240] := ABS(SRC[255:240])

image/svg+xmlVPABSW (EVEX encoded versions)(KL, VL) = (8, 128), (16, 256), (32, 512)FOR j := 0 TO KL-1i := j * 16IF k1[j] OR *no writemask*THEN Unsigned DEST[i+15:i] := ABS(SRC[i+15:i])ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+15:i] remains unchanged*ELSE *zeroing-masking*; zeroing-maskingDEST[i+15:i] := 0FIFI;ENDFOR;DEST[MAXVL-1:VL] := 0PABSD with 128 bit operands:Unsigned DEST[31:0] := ABS(SRC[31:0]) Repeat operation for 2nd through 3rd 32-bit double words Unsigned DEST[127:96] := ABS(SRC[127:96]) VPABSD with 128 bit operands:Unsigned DEST[31:0] := ABS(SRC[31:0]) Repeat operation for 2nd through 3rd 32-bit double words Unsigned DEST[127:96] := ABS(SRC[127:96]) VPABSD with 256 bit operands:Unsigned DEST[31:0] := ABS(SRC[31:0]) Repeat operation for 2nd through 7th 32-bit double words Unsigned DEST[255:224] := ABS(SRC[255:224]) VPABSD (EVEX encoded versions)(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no writemask*THEN IF (EVEX.b = 1) AND (SRC *is memory*)THENUnsigned DEST[i+31:i] := ABS(SRC[31:0])ELSE Unsigned DEST[i+31:i] := ABS(SRC[i+31:i])FI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE *zeroing-masking*; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFOR;DEST[MAXVL-1:VL] := 0

image/svg+xmlVPABSQ (EVEX encoded versions)(KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64IF k1[j] OR *no writemask*THEN IF (EVEX.b = 1) AND (SRC *is memory*)THENUnsigned DEST[i+63:i] := ABS(SRC[63:0])ELSE Unsigned DEST[i+63:i] := ABS(SRC[i+63:i])FI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+63:i] remains unchanged*ELSE *zeroing-masking*; zeroing-maskingDEST[i+63:i] := 0FIFI;ENDFOR;DEST[MAXVL-1:VL] := 0Intel C/C++ Compiler Intrinsic EquivalentsVPABSB__m512i _mm512_abs_epi8 ( __m512i a)VPABSW__m512i _mm512_abs_epi16 ( __m512i a)VPABSB__m512i _mm512_mask_abs_epi8 ( __m512i s, __mmask64 m, __m512i a)VPABSW__m512i _mm512_mask_abs_epi16 ( __m512i s, __mmask32 m, __m512i a)VPABSB__m512i _mm512_maskz_abs_epi8 (__mmask64 m, __m512i a)VPABSW__m512i _mm512_maskz_abs_epi16 (__mmask32 m, __m512i a)VPABSB__m256i _mm256_mask_abs_epi8 (__m256i s, __mmask32 m, __m256i a)VPABSW__m256i _mm256_mask_abs_epi16 (__m256i s, __mmask16 m, __m256i a)VPABSB__m256i _mm256_maskz_abs_epi8 (__mmask32 m, __m256i a)VPABSW__m256i _mm256_maskz_abs_epi16 (__mmask16 m, __m256i a)VPABSB__m128i _mm_mask_abs_epi8 (__m128i s, __mmask16 m, __m128i a)VPABSW__m128i _mm_mask_abs_epi16 (__m128i s, __mmask8 m, __m128i a)VPABSB__m128i _mm_maskz_abs_epi8 (__mmask16 m, __m128i a)VPABSW__m128i _mm_maskz_abs_epi16 (__mmask8 m, __m128i a)VPABSD __m256i _mm256_mask_abs_epi32(__m256i s, __mmask8 k, __m256i a);VPABSD __m256i _mm256_maskz_abs_epi32( __mmask8 k, __m256i a);VPABSD __m128i _mm_mask_abs_epi32(__m128i s, __mmask8 k, __m128i a);VPABSD __m128i _mm_maskz_abs_epi32( __mmask8 k, __m128i a);VPABSD __m512i _mm512_abs_epi32( __m512i a);VPABSD __m512i _mm512_mask_abs_epi32(__m512i s, __mmask16 k, __m512i a);VPABSD __m512i _mm512_maskz_abs_epi32( __mmask16 k, __m512i a);VPABSQ __m512i _mm512_abs_epi64( __m512i a);VPABSQ __m512i _mm512_mask_abs_epi64(__m512i s, __mmask8 k, __m512i a);VPABSQ __m512i _mm512_maskz_abs_epi64( __mmask8 k, __m512i a);VPABSQ __m256i _mm256_mask_abs_epi64(__m256i s, __mmask8 k, __m256i a);VPABSQ __m256i _mm256_maskz_abs_epi64( __mmask8 k, __m256i a);VPABSQ __m128i _mm_mask_abs_epi64(__m128i s, __mmask8 k, __m128i a);VPABSQ __m128i _mm_maskz_abs_epi64( __mmask8 k, __m128i a);PABSB __m128i _mm_abs_epi8 (__m128i a)VPABSB __m128i _mm_abs_epi8 (__m128i a)

image/svg+xmlVPABSB __m256i _mm256_abs_epi8 (__m256i a)PABSW __m128i _mm_abs_epi16 (__m128i a)VPABSW __m128i _mm_abs_epi16 (__m128i a)VPABSW __m256i _mm256_abs_epi16 (__m256i a)PABSD __m128i _mm_abs_epi32 (__m128i a)VPABSD __m128i _mm_abs_epi32 (__m128i a)VPABSD __m256i _mm256_abs_epi32 (__m256i a)SIMD Floating-Point ExceptionsNoneOther ExceptionsNon-EVEX-encoded instruction, see Table2-21, “Type 4 Class Exception Conditions”.EVEX-encoded VPABSD/Q, see Table2-49, “Type E4 Class Exception Conditions”.EVEX-encoded VPABSB/W, see Exceptions Type E4.nb in Table2-49, “Type E4 Class Exception Conditions”.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.