image/svg+xmlOR—Logical Inclusive ORInstruction Operand EncodingDescriptionPerforms a bitwise inclusive OR operation between the destination (first) and source (second) operands and stores the result in the destination operand location. The source operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location. (However, two memory operands cannot be used in one instruction.) Each bit of the result of the OR instruction is set to 0 if both corresponding bits of the first and second operands are 0; otherwise, each bit is set to 1.This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.OpcodeInstructionOp/ En64-Bit ModeCompat/Leg ModeDescription0C ibOR AL, imm8IValidValidAL OR imm8.0D iwOR AX, imm16IValidValidAX OR imm16.0D idOR EAX, imm32IValidValidEAX OR imm32.REX.W + 0D idOR RAX, imm32IValidN.E.RAX OR imm32 (sign-extended).80 /1 ibOR r/m8, imm8MIValidValidr/m8 OR imm8.REX + 80 /1 ibOR r/m8*, imm8MIValidN.E.r/m8 OR imm8.81 /1 iwOR r/m16, imm16MIValidValid r/m16 OR imm16.81 /1 idOR r/m32, imm32MIValidValid r/m32 OR imm32.REX.W + 81 /1 idOR r/m64, imm32MIValidN.E. r/m64 OR imm32 (sign-extended).83 /1 ibOR r/m16, imm8MIValidValidr/m16 OR imm8 (sign-extended).83 /1 ibOR r/m32, imm8MIValidValidr/m32 OR imm8 (sign-extended).REX.W + 83 /1 ibOR r/m64, imm8MIValidN.E.r/m64 OR imm8 (sign-extended).08 /rOR r/m8, r8MRValidValidr/m8 OR r8.REX + 08 /rOR r/m8*, r8*MRValidN.E.r/m8 OR r8.09 /rOR r/m16, r16MRValidValidr/m16 OR r16.09 /rOR r/m32, r32MRValidValidr/m32 OR r32.REX.W + 09 /rOR r/m64, r64MRValidN.E.r/m64 OR r64.0A /rOR r8, r/m8RMValidValidr8 OR r/m8.REX + 0A /rOR r8*, r/m8*RMValidN.E.r8 OR r/m8.0B /rOR r16, r/m16RMValidValidr16 OR r/m16.0B /rOR r32, r/m32RMValidValidr32 OR r/m32.REX.W + 0B /rOR r64, r/m64RMValid N.E.r64 OR r/m64.NOTES:*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. Op/EnOperand 1Operand 2Operand 3Operand 4IAL/AX/EAX/RAXimm8/16/32NANAMIModRM:r/m (r, w)imm8/16/32NANAMRModRM:r/m (r, w)ModRM:reg (r)NANARMModRM:reg (r, w)ModRM:r/m (r)NANA

image/svg+xmlIn 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.OperationDEST := DEST OR SRC;Flags AffectedThe OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is undefined.Protected Mode Exceptions#GP(0)If the destination operand points to a non-writable segment.If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used but the destination is not a memory operand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used but the destination is not a memory operand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made.#UD If the LOCK prefix is used but the destination is not a memory operand.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used but the destination is not a memory operand.

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