image/svg+xmlMULX — Unsigned Multiply Without Affecting FlagsInstruction Operand EncodingDescription Performs an unsigned multiplication of the implicit source operand (EDX/RDX) and the specified source operand (the third operand) and stores the low half of the result in the second destination (second operand), the high half of the result in the first destination operand (first operand), without reading or writing the arithmetic flags. This enables efficient programming where the software can interleave add with carry operations and multiplications. If the first and second operand are identical, it will contain the high half of the multiplication result.This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.Operation// DEST1: ModRM:reg// DEST2: VEX.vvvvIF (OperandSize = 32)SRC1 := EDX;DEST2 := (SRC1*SRC2)[31:0];DEST1 := (SRC1*SRC2)[63:32];ELSE IF (OperandSize = 64)SRC1 := RDX;DEST2 := (SRC1*SRC2)[63:0];DEST1 := (SRC1*SRC2)[127:64];FIFlags AffectedNoneIntel C/C++ Compiler Intrinsic EquivalentAuto-generated from high-level language when possible.unsigned int mulx_u32(unsigned int a, unsigned int b, unsigned int * hi);unsigned __int64 mulx_u64(unsigned __int64 a, unsigned __int64 b, unsigned __int64 * hi);SIMD Floating-Point ExceptionsNoneOpcode/InstructionOp/ En64/32-bit ModeCPUID Feature FlagDescriptionVEX.LZ.F2.0F38.W0 F6 /rMULX r32a, r32b, r/m32RVMV/VBMI2Unsigned multiply of r/m32 with EDX without affecting arithmetic flags.VEX.LZ.F2.0F38.W1 F6 /rMULX r64a, r64b, r/m64RVMV/N.E.BMI2Unsigned multiply of r/m64 with RDX without affecting arithmetic flags.Op/EnOperand 1Operand 2Operand 3Operand 4RVMModRM:reg (w)VEX.vvvv (w)ModRM:r/m (r)RDX/EDX is implied 64/32 bits source

image/svg+xmlOther ExceptionsSee Table2-29, “Type 13 Class Exception Conditions”.

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