MULSS—Multiply Scalar Single-Precision Floating-Point ValuesInstruction Operand EncodingDescriptionMultiplies the low single-precision floating-point value from the second source operand by the low single-precision floating-point value in the first source operand, and stores the single-precision floating-point result in the destina-tion operand. The second source operand can be an XMM register or a 32-bit memory location. The first source operand and the destination operands are XMM registers. 128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL-1:32) of the corresponding YMM destination register remain unchanged.VEX.128 and EVEX encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The three high-order doublewords of the destination operand are copied from the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.EVEX encoded version: The low doubleword element of the destination operand is updated according to the writemask.Software should ensure VMULSS is encoded with VEX.L=0. Encoding VMULSS with VEX.L=1 may encounter unpre-dictable behavior across different processor generations.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionF3 0F 59 /rMULSS xmm1,xmm2/m32AV/VSSEMultiply the low single-precision floating-point value in xmm2/m32 by the low single-precision floating-point value in xmm1.VEX.LIG.F3.0F.WIG 59 /rVMULSS xmm1,xmm2, xmm3/m32BV/VAVXMultiply the low single-precision floating-point value in xmm3/m32 by the low single-precision floating-point value in xmm2.EVEX.LLIG.F3.0F.W0 59 /rVMULSS xmm1 {k1}{z}, xmm2, xmm3/m32 {er}CV/VAVX512FMultiply the low single-precision floating-point value in xmm3/m32 by the low single-precision floating-point value in xmm2.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACTuple1 ScalarModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA
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