MULSD—Multiply Scalar Double-Precision Floating-Point ValueInstruction Operand EncodingDescriptionMultiplies the low double-precision floating-point value in the second source operand by the low double-precision floating-point value in the first source operand, and stores the double-precision floating-point result in the destina-tion operand. The second source operand can be an XMM register or a 64-bit memory location. The first source operand and the destination operands are XMM registers. 128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL-1:64) of the corresponding destination register remain unchanged.VEX.128 and EVEX encoded version: The quadword at bits 127:64 of the destination operand is copied from the same bits of the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.EVEX encoded version: The low quadword element of the destination operand is updated according to the writemask.Software should ensure VMULSD is encoded with VEX.L=0. Encoding VMULSD with VEX.L=1 may encounter unpre-dictable behavior across different processor generations.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionF2 0F 59 /rMULSD xmm1,xmm2/m64AV/VSSE2Multiply the low double-precision floating-point value in xmm2/m64 by low double-precision floating-point value in xmm1.VEX.LIG.F2.0F.WIG 59 /rVMULSD xmm1,xmm2, xmm3/m64BV/VAVXMultiply the low double-precision floating-point value in xmm3/m64 by low double-precision floating-point value in xmm2.EVEX.LLIG.F2.0F.W1 59 /rVMULSD xmm1 {k1}{z}, xmm2, xmm3/m64 {er}CV/VAVX512FMultiply the low double-precision floating-point value in xmm3/m64 by low double-precision floating-point value in xmm2.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACTuple1 ScalarModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA
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