image/svg+xmlMUL—Unsigned MultiplyInstruction Operand EncodingDescriptionPerforms an unsigned multiplication of the first operand (destination operand) and the second operand (source operand) and stores the result in the destination operand. The destination operand is an implied operand located in register AL, AX or EAX (depending on the size of the operand); the source operand is located in a general-purpose register or a memory location. The action of this instruction and the location of the result depends on the opcode and the operand size as shown in Table 4-9.The result is stored in register AX, register pair DX:AX, or register pair EDX:EAX (depending on the operand size), with the high-order bits of the product contained in register AH, DX, or EDX, respectively. If the high-order bits of the product are 0, the CF and OF flags are cleared; otherwise, the flags are set.In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to addi-tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.OpcodeInstructionOp/ En64-Bit ModeCompat/Leg ModeDescriptionF6 /4MUL r/m8MValidValidUnsigned multiply (AX := AL ∗ r/m8).REX + F6 /4MUL r/m8*MValidN.E.Unsigned multiply (AX := AL ∗ r/m8).F7 /4MUL r/m16MValidValidUnsigned multiply (DX:AX := AX ∗ r/m16).F7 /4MUL r/m32MValidValidUnsigned multiply (EDX:EAX := EAX ∗ r/m32).REX.W + F7 /4MUL r/m64MValid N.E.Unsigned multiply (RDX:RAX := RAX ∗ r/m64).NOTES:*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. Op/EnOperand 1Operand 2Operand 3Operand 4MModRM:r/m (r)NANANATable 4-9. MUL ResultsOperand SizeSource 1Source 2DestinationByteALr/m8AXWordAXr/m16DX:AXDoublewordEAXr/m32EDX:EAXQuadwordRAXr/m64RDX:RAX

image/svg+xmlOperationIF (Byte operation)THEN AX := AL ∗ SRC;ELSE (* Word or doubleword operation *)IF OperandSize = 16THEN DX:AX := AX ∗ SRC;ELSE IF OperandSize = 32THEN EDX:EAX := EAX ∗ SRC; FI;ELSE (* OperandSize = 64 *)RDX:RAX := RAX ∗ SRC;FI;FI;Flags AffectedThe OF and CF flags are set to 0 if the upper half of the result is 0; otherwise, they are set to 1. The SF, ZF, AF, and PF flags are undefined.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made.#UD If the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.