image/svg+xmlMOVUPS—Move Unaligned Packed Single-Precision Floating-Point ValuesInstruction Operand EncodingDescriptionNote: VEX.vvvv and EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.EVEX.512 encoded version:Moves 512 bits of packed single-precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load a ZMM register from a 512-bit float32 memory location, to store the contents of a ZMM register into memory. The destination operand is updated according to the writemask.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F 10 /rMOVUPS xmm1, xmm2/m128AV/VSSEMove unaligned packed single-precision floating-point from xmm2/mem to xmm1.NP 0F 11 /rMOVUPS xmm2/m128, xmm1BV/VSSEMove unaligned packed single-precision floating-point from xmm1 to xmm2/mem.VEX.128.0F.WIG 10 /rVMOVUPS xmm1, xmm2/m128AV/VAVXMove unaligned packed single-precision floating-point from xmm2/mem to xmm1.VEX.128.0F.WIG 11 /rVMOVUPS xmm2/m128, xmm1BV/VAVXMove unaligned packed single-precision floating-point from xmm1 to xmm2/mem.VEX.256.0F.WIG 10 /rVMOVUPS ymm1, ymm2/m256AV/VAVXMove unaligned packed single-precision floating-point from ymm2/mem to ymm1.VEX.256.0F.WIG 11 /rVMOVUPS ymm2/m256, ymm1BV/VAVXMove unaligned packed single-precision floating-point from ymm1 to ymm2/mem.EVEX.128.0F.W0 10 /rVMOVUPS xmm1 {k1}{z}, xmm2/m128CV/VAVX512VLAVX512FMove unaligned packed single-precision floating-point values from xmm2/m128 to xmm1 using writemask k1.EVEX.256.0F.W0 10 /rVMOVUPS ymm1 {k1}{z}, ymm2/m256CV/VAVX512VLAVX512FMove unaligned packed single-precision floating-point values from ymm2/m256 to ymm1 using writemask k1.EVEX.512.0F.W0 10 /rVMOVUPS zmm1 {k1}{z}, zmm2/m512CV/VAVX512FMove unaligned packed single-precision floating-point values from zmm2/m512 to zmm1 using writemask k1.EVEX.128.0F.W0 11 /rVMOVUPS xmm2/m128 {k1}{z}, xmm1DV/VAVX512VLAVX512FMove unaligned packed single-precision floating-point values from xmm1 to xmm2/m128 using writemask k1.EVEX.256.0F.W0 11 /rVMOVUPS ymm2/m256 {k1}{z}, ymm1DV/VAVX512VLAVX512FMove unaligned packed single-precision floating-point values from ymm1 to ymm2/m256 using writemask k1.EVEX.512.0F.W0 11 /rVMOVUPS zmm2/m512 {k1}{z}, zmm1DV/VAVX512FMove unaligned packed single-precision floating-point values from zmm1 to zmm2/m512 using writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)NANABNAModRM:r/m (w)ModRM:reg (r)NANACFull MemModRM:reg (w)ModRM:r/m (r)NANADFull MemModRM:r/m (w)ModRM:reg (r)NANA

image/svg+xmlVEX.256 and EVEX.256 encoded versions:Moves 256 bits of packed single-precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM registers. Bits (MAXVL-1:256) of the destination register are zeroed.128-bit versions:Moves 128 bits of packed single-precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers. 128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding destination register remain unchanged.When the source or destination operand is a memory operand, the operand may be unaligned without causing a general-protection exception (#GP) to be generated.VEX.128 and EVEX.128 encoded versions: Bits (MAXVL-1:128) of the destination register are zeroed.OperationVMOVUPS (EVEX encoded versions, register-copy form)(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no writemask*THEN DEST[i+31:i] := SRC[i+31:i]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE DEST[i+31:i] := 0 ; zeroing-maskingFIFI;ENDFORDEST[MAXVL-1:VL] := 0VMOVUPS (EVEX encoded versions, store-form) (KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no writemask*THEN DEST[i+31:i] := SRC[i+31:i]ELSE *DEST[i+31:i] remains unchanged*; merging-maskingFI;ENDFOR;

image/svg+xmlVMOVUPS (EVEX encoded versions, load-form) (KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no writemask*THEN DEST[i+31:i] := SRC[i+31:i]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE DEST[i+31:i] := 0 ; zeroing-maskingFIFI;ENDFORDEST[MAXVL-1:VL] := 0VMOVUPS (VEX.256 encoded version, load - and register copy)DEST[255:0] := SRC[255:0]DEST[MAXVL-1:256] := 0VMOVUPS (VEX.256 encoded version, store-form)DEST[255:0] := SRC[255:0]VMOVUPS (VEX.128 encoded version)DEST[127:0] := SRC[127:0]DEST[MAXVL-1:128] := 0MOVUPS (128-bit load- and register-copy- form Legacy SSE version)DEST[127:0] := SRC[127:0]DEST[MAXVL-1:128] (Unmodified)(V)MOVUPS (128-bit store-form version)DEST[127:0] := SRC[127:0]Intel C/C++ Compiler Intrinsic EquivalentVMOVUPS __m512 _mm512_loadu_ps( void * s);VMOVUPS __m512 _mm512_mask_loadu_ps(__m512 a, __mmask16 k, void * s);VMOVUPS __m512 _mm512_maskz_loadu_ps( __mmask16 k, void * s);VMOVUPS void _mm512_storeu_ps( void * d, __m512 a);VMOVUPS void _mm512_mask_storeu_ps( void * d, __mmask8 k, __m512 a);VMOVUPS __m256 _mm256_mask_loadu_ps(__m256 a, __mmask8 k, void * s);VMOVUPS __m256 _mm256_maskz_loadu_ps( __mmask8 k, void * s);VMOVUPS void _mm256_mask_storeu_ps( void * d, __mmask8 k, __m256 a);VMOVUPS __m128 _mm_mask_loadu_ps(__m128 a, __mmask8 k, void * s);VMOVUPS __m128 _mm_maskz_loadu_ps( __mmask8 k, void * s);VMOVUPS void _mm_mask_storeu_ps( void * d, __mmask8 k, __m128 a);MOVUPS __m256 _mm256_loadu_ps ( float * p);MOVUPS void _mm256 _storeu_ps( float *p, __m256 a);MOVUPS __m128 _mm_loadu_ps ( float * p);MOVUPS void _mm_storeu_ps( float *p, __m128 a);SIMD Floating-Point ExceptionsNone

image/svg+xmlOther ExceptionsNon-EVEX-encoded instruction, see Table2-21, “Type 4 Class Exception Conditions”.Note treatment of #AC varies. EVEX-encoded instruction, see Exceptions Type E4.nb in Table2-49, “Type E4 Class Exception Conditions”.Additionally:#UDIf EVEX.vvvv != 1111B or VEX.vvvv != 1111B.

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