image/svg+xmlMOVUPD—Move Unaligned Packed Double-Precision Floating-Point ValuesInstruction Operand EncodingDescriptionNote: VEX.vvvv and EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.EVEX.512 encoded version:Moves 512 bits of packed double-precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load a ZMM register from a float64 memory location, to store the contents of a ZMM register into a memory. The destination operand is updated according to the writemask.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F 10 /rMOVUPD xmm1, xmm2/m128AV/VSSE2Move unaligned packed double-precision floating-point from xmm2/mem to xmm1.66 0F 11 /rMOVUPD xmm2/m128, xmm1BV/VSSE2Move unaligned packed double-precision floating-point from xmm1 to xmm2/mem.VEX.128.66.0F.WIG 10 /rVMOVUPD xmm1, xmm2/m128AV/VAVXMove unaligned packed double-precision floating-point from xmm2/mem to xmm1.VEX.128.66.0F.WIG 11 /rVMOVUPD xmm2/m128, xmm1BV/VAVXMove unaligned packed double-precision floating-point from xmm1 to xmm2/mem.VEX.256.66.0F.WIG 10 /rVMOVUPD ymm1, ymm2/m256AV/VAVXMove unaligned packed double-precision floating-point from ymm2/mem to ymm1.VEX.256.66.0F.WIG 11 /rVMOVUPD ymm2/m256, ymm1BV/VAVXMove unaligned packed double-precision floating-point from ymm1 to ymm2/mem.EVEX.128.66.0F.W1 10 /rVMOVUPD xmm1 {k1}{z}, xmm2/m128CV/VAVX512VLAVX512FMove unaligned packed double-precision floating-point from xmm2/m128 to xmm1 using writemask k1.EVEX.128.66.0F.W1 11 /rVMOVUPD xmm2/m128 {k1}{z}, xmm1DV/VAVX512VLAVX512FMove unaligned packed double-precision floating-point from xmm1 to xmm2/m128 using writemask k1.EVEX.256.66.0F.W1 10 /rVMOVUPD ymm1 {k1}{z}, ymm2/m256CV/VAVX512VLAVX512FMove unaligned packed double-precision floating-point from ymm2/m256 to ymm1 using writemask k1.EVEX.256.66.0F.W1 11 /rVMOVUPD ymm2/m256 {k1}{z}, ymm1DV/VAVX512VLAVX512FMove unaligned packed double-precision floating-point from ymm1 to ymm2/m256 using writemask k1.EVEX.512.66.0F.W1 10 /rVMOVUPD zmm1 {k1}{z}, zmm2/m512CV/VAVX512FMove unaligned packed double-precision floating-point values from zmm2/m512 to zmm1 using writemask k1.EVEX.512.66.0F.W1 11 /rVMOVUPD zmm2/m512 {k1}{z}, zmm1DV/VAVX512FMove unaligned packed double-precision floating-point values from zmm1 to zmm2/m512 using writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)NANABNAModRM:r/m (w)ModRM:reg (r)NANACFull MemModRM:reg (w)ModRM:r/m (r)NANADFull MemModRM:r/m (w)ModRM:reg (r)NANA

image/svg+xmlVEX.256 encoded version:Moves 256 bits of packed double-precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM registers. Bits (MAXVL-1:256) of the destination register are zeroed.128-bit versions:Moves 128 bits of packed double-precision floating-point values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers. 128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding destination register remain unchanged.When the source or destination operand is a memory operand, the operand may be unaligned on a 16-byte boundary without causing a general-protection exception (#GP) to be generatedVEX.128 and EVEX.128 encoded versions: Bits (MAXVL-1:128) of the destination register are zeroed.OperationVMOVUPD (EVEX encoded versions, register-copy form)(KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64IF k1[j] OR *no writemask*THEN DEST[i+63:i] := SRC[i+63:i]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+63:i] remains unchanged*ELSE DEST[i+63:i] := 0 ; zeroing-maskingFIFI;ENDFORDEST[MAXVL-1:VL] := 0VMOVUPD (EVEX encoded versions, store-form) (KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64IF k1[j] OR *no writemask*THEN DEST[i+63:i] := SRC[i+63:i]ELSE *DEST[i+63:i] remains unchanged*; merging-maskingFI;ENDFOR;

image/svg+xmlVMOVUPD (EVEX encoded versions, load-form) (KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64IF k1[j] OR *no writemask*THEN DEST[i+63:i] := SRC[i+63:i]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+63:i] remains unchanged*ELSE DEST[i+63:i] := 0 ; zeroing-maskingFIFI;ENDFORDEST[MAXVL-1:VL] := 0VMOVUPD (VEX.256 encoded version, load - and register copy)DEST[255:0] := SRC[255:0]DEST[MAXVL-1:256] := 0VMOVUPD (VEX.256 encoded version, store-form)DEST[255:0] := SRC[255:0]VMOVUPD (VEX.128 encoded version)DEST[127:0] := SRC[127:0]DEST[MAXVL-1:128] := 0MOVUPD (128-bit load- and register-copy- form Legacy SSE version)DEST[127:0] := SRC[127:0]DEST[MAXVL-1:128] (Unmodified)(V)MOVUPD (128-bit store-form version)DEST[127:0] := SRC[127:0]Intel C/C++ Compiler Intrinsic EquivalentVMOVUPD __m512d _mm512_loadu_pd( void * s);VMOVUPD __m512d _mm512_mask_loadu_pd(__m512d a, __mmask8 k, void * s);VMOVUPD __m512d _mm512_maskz_loadu_pd( __mmask8 k, void * s);VMOVUPD void _mm512_storeu_pd( void * d, __m512d a);VMOVUPD void _mm512_mask_storeu_pd( void * d, __mmask8 k, __m512d a);VMOVUPD __m256d _mm256_mask_loadu_pd(__m256d s, __mmask8 k, void * m);VMOVUPD __m256d _mm256_maskz_loadu_pd( __mmask8 k, void * m);VMOVUPD void _mm256_mask_storeu_pd( void * d, __mmask8 k, __m256d a);VMOVUPD __m128d _mm_mask_loadu_pd(__m128d s, __mmask8 k, void * m);VMOVUPD __m128d _mm_maskz_loadu_pd( __mmask8 k, void * m);VMOVUPD void _mm_mask_storeu_pd( void * d, __mmask8 k, __m128d a);MOVUPD __m256d _mm256_loadu_pd (double * p);MOVUPD void _mm256_storeu_pd( double *p, __m256d a);MOVUPD __m128d _mm_loadu_pd (double * p);MOVUPD void _mm_storeu_pd( double *p, __m128d a);SIMD Floating-Point ExceptionsNone

image/svg+xmlOther ExceptionsNon-EVEX-encoded instruction, see Table2-21, “Type 4 Class Exception Conditions”.Note treatment of #AC varies; additionally:#UDIf VEX.vvvv != 1111B.EVEX-encoded instruction, see Exceptions Type E4.nb in Table2-49, “Type E4 Class Exception Conditions”.

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