image/svg+xmlMOVSX/MOVSXD—Move with Sign-ExtensionInstruction Operand EncodingDescriptionCopies the contents of the source operand (register or memory location) to the destination operand (register) and sign extends the value to 16 or 32 bits (see Figure 7-6 in the Intel® 64 and IA-32 Architectures Software Devel-oper’s Manual, Volume 1). The size of the converted value depends on the operand-size attribute.In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to addi-tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.OperationDEST := SignExtend(SRC);Flags AffectedNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.OpcodeInstructionOp/ En64-Bit ModeCompat/Leg ModeDescription0F BE /rMOVSX r16, r/m8RMValidValidMove byte to word with sign-extension.0F BE /rMOVSX r32, r/m8RMValidValidMove byte to doubleword with sign-extension.REX.W + 0F BE /rMOVSX r64, r/m8RMValidN.E.Move byte to quadword with sign-extension.0F BF /rMOVSX r32, r/m16RMValidValidMove word to doubleword, with sign-extension.REX.W + 0F BF /rMOVSX r64, r/m16RMValid N.E.Move word to quadword with sign-extension.63 /r*MOVSXD r16, r/m16RMValid N.E.Move word to word with sign-extension.63 /r*MOVSXD r32, r/m32RMValid N.E.Move doubleword to doubleword with sign-extension.REX.W + 63 /rMOVSXD r64, r/m32RMValid N.E.Move doubleword to quadword with sign-extension.NOTES:*The use of MOVSXD without REX.W in 64-bit mode is discouraged. Regular MOV should be used instead of using MOVSXD without REX.W. Op/EnOperand 1Operand 2Operand 3Operand 4RMModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlReal-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#UD If the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.