image/svg+xmlMOVSS—Move or Merge Scalar Single-Precision Floating-Point ValueInstruction Operand EncodingOpcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionF3 0F 10 /rMOVSS xmm1, xmm2AV/VSSEMerge scalar single-precision floating-point value from xmm2 to xmm1 register.F3 0F 10 /rMOVSS xmm1, m32AV/VSSELoad scalar single-precision floating-point value from m32 to xmm1 register.VEX.LIG.F3.0F.WIG 10 /rVMOVSS xmm1, xmm2, xmm3BV/VAVXMerge scalar single-precision floating-point value from xmm2 and xmm3 to xmm1 registerVEX.LIG.F3.0F.WIG 10 /rVMOVSS xmm1, m32DV/VAVXLoad scalar single-precision floating-point value from m32 to xmm1 register.F3 0F 11 /rMOVSS xmm2/m32, xmm1CV/VSSEMove scalar single-precision floating-point value from xmm1 register to xmm2/m32.VEX.LIG.F3.0F.WIG 11 /rVMOVSS xmm1, xmm2, xmm3EV/VAVXMove scalar single-precision floating-point value from xmm2 and xmm3 to xmm1 register.VEX.LIG.F3.0F.WIG 11 /rVMOVSS m32, xmm1CV/VAVXMove scalar single-precision floating-point value from xmm1 register to m32.EVEX.LLIG.F3.0F.W0 10 /rVMOVSS xmm1 {k1}{z}, xmm2, xmm3BV/VAVX512FMove scalar single-precision floating-point value from xmm2 and xmm3 to xmm1 register under writemask k1.EVEX.LLIG.F3.0F.W0 10 /rVMOVSS xmm1 {k1}{z}, m32FV/VAVX512FMove scalar single-precision floating-point values from m32 to xmm1 under writemask k1.EVEX.LLIG.F3.0F.W0 11 /rVMOVSS xmm1 {k1}{z}, xmm2, xmm3EV/VAVX512FMove scalar single-precision floating-point value from xmm2 and xmm3 to xmm1 register under writemask k1.EVEX.LLIG.F3.0F.W0 11 /rVMOVSS m32 {k1}, xmm1GV/VAVX512FMove scalar single-precision floating-point values from xmm1 to m32 under writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACNAModRM:r/m (w)ModRM:reg (r)NANADNAModRM:reg (w)ModRM:r/m (r)NANAENAModRM:r/m (w)EVEX.vvvv (r)ModRM:reg (r)NAFTuple1 ScalarModRM:reg (r, w)ModRM:r/m (r)NANAGTuple1 ScalarModRM:r/m (w)ModRM:reg (r)NANA

image/svg+xmlDescriptionMoves a scalar single-precision floating-point value from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be XMM registers or 32-bit memory locations. This instruction can be used to move a single-precision floating-point value to and from the low doubleword of an XMM register and a 32-bit memory location, or to move a single-precision floating-point value between the low doublewords of two XMM registers. The instruction cannot be used to transfer data between memory locations.Legacy version: When the source and destination operands are XMM registers, bits (MAXVL-1:32) of the corre-sponding destination register are unmodified. When the source operand is a memory location and destination operand is an XMM registers, Bits (127:32) of the destination operand is cleared to all 0s, bits MAXVL:128 of the destination operand remains unchanged. VEX and EVEX encoded register-register syntax: Moves a scalar single-precision floating-point value from the second source operand (the third operand) to the low doubleword element of the destination operand (the first operand). Bits 127:32 of the destination operand are copied from the first source operand (the second operand). Bits (MAXVL-1:128) of the corresponding destination register are zeroed.VEX and EVEX encoded memory load syntax: When the source operand is a memory location and destination operand is an XMM registers, bits MAXVL:32 of the destination operand is cleared to all 0s.EVEX encoded versions: The low doubleword of the destination is updated according to the writemask.Note: For memory store form instruction “VMOVSS m32, xmm1”, VEX.vvvv is reserved and must be 1111b other-wise instruction will #UD. For memory store form instruction “VMOVSS mv {k1}, xmm1”, EVEX.vvvv is reserved and must be 1111b otherwise instruction will #UD.Software should ensure VMOVSS is encoded with VEX.L=0. Encoding VMOVSS with VEX.L=1 may encounter unpredictable behavior across different processor generations.OperationVMOVSS (EVEX.LLIG.F3.0F.W0 11 /r when the source operand is memory and the destination is an XMM register)IF k1[0] or *no writemask*THENDEST[31:0] := SRC[31:0]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[31:0] remains unchanged*ELSE ; zeroing-maskingTHEN DEST[31:0] := 0FI;FI;DEST[MAXVL-1:32] := 0VMOVSS (EVEX.LLIG.F3.0F.W0 10 /r when the source operand is an XMM register and the destination is memory)IF k1[0] or *no writemask*THENDEST[31:0] := SRC[31:0]ELSE*DEST[31:0] remains unchanged* ; merging-maskingFI;

image/svg+xmlVMOVSS (EVEX.LLIG.F3.0F.W0 10/11 /r where the source and destination are XMM registers)IF k1[0] or *no writemask*THENDEST[31:0] := SRC2[31:0]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[31:0] remains unchanged*ELSE ; zeroing-maskingTHEN DEST[31:0] := 0FI;FI;DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0MOVSS (Legacy SSE version when the source and destination operands are both XMM registers)DEST[31:0] := SRC[31:0]DEST[MAXVL-1:32] (Unmodified)VMOVSS (VEX.128.F3.0F 11 /r where the destination is an XMM register)DEST[31:0] := SRC2[31:0]DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0VMOVSS (VEX.128.F3.0F 10 /r where the source and destination are XMM registers)DEST[31:0] := SRC2[31:0]DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0VMOVSS (VEX.128.F3.0F 10 /r when the source operand is memory and the destination is an XMM register)DEST[31:0] := SRC[31:0]DEST[MAXVL-1:32] := 0MOVSS/VMOVSS (when the source operand is an XMM register and the destination is memory)DEST[31:0] := SRC[31:0]MOVSS (Legacy SSE version when the source operand is memory and the destination is an XMM register)DEST[31:0] := SRC[31:0]DEST[127:32] := 0DEST[MAXVL-1:128] (Unmodified)Intel C/C++ Compiler Intrinsic EquivalentVMOVSS __m128 _mm_mask_load_ss(__m128 s, __mmask8 k, float * p); VMOVSS __m128 _mm_maskz_load_ss( __mmask8 k, float * p); VMOVSS __m128 _mm_mask_move_ss(__m128 sh, __mmask8 k, __m128 sl, __m128 a); VMOVSS __m128 _mm_maskz_move_ss( __mmask8 k, __m128 s, __m128 a); VMOVSS void _mm_mask_store_ss(float * p, __mmask8 k, __m128 a); MOVSS __m128 _mm_load_ss(float * p)MOVSS void_mm_store_ss(float * p, __m128 a)MOVSS __m128 _mm_move_ss(__m128 a, __m128 b)SIMD Floating-Point ExceptionsNone

image/svg+xmlOther ExceptionsNon-EVEX-encoded instruction, see Table2-22, “Type 5 Class Exception Conditions”; additionally:#UDIf VEX.vvvv != 1111B.EVEX-encoded instruction, see Table2-58, “Type E10 Class Exception Conditions”.

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