image/svg+xml MOVQ2DQ—Move Quadword from MMX Technology to XMM Register Instruction Operand Encoding Description Moves the quadword from the source operand (second operand) to the low quadword of the destination operand (first operand). The source operand is an MMX technology register and the destination operand is an XMM register. This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the MOVQ2DQ instruction is executed. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[63:0] := SRC[63:0]; DEST[127:64] := 00000000000000000H; Intel C/C ++ Compiler Intrinsic Equivalent MOVQ2DQ:__128i _mm_movpi64_epi64 ( __m64 a) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #NMIf CR0.TS[bit 3] = 1. #UDIf CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. #MFIf there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in protected mode. Virtual-8086 Mode Exceptions Same exceptions as in protected mode. Compatibility Mode Exceptions Same exceptions as in protected mode. Opcode / Instruction Op/ En 64/32-bit Mode CPUID Feature Flag Description F3 0F D6 /r MOVQ2DQ xmm , mm RMV/VSSE2Move quadword from mmx to low quadword of xmm . Op/EnOperand 1Operand 2Operand 3Operand 4 RMModRM:reg (w)ModRM:r/m (r)NANA image/svg+xml 64-Bit Mode Exceptions Same exceptions as in protected mode. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .