image/svg+xmlMOVNTDQ—Store Packed Integers Using Non-Temporal HintInstruction Operand Encoding1DescriptionMoves the packed integers in the source operand (second operand) to the destination operand (first operand) using a non-temporal hint to prevent caching of the data during the write to memory. The source operand is an XMM register, YMM register or ZMM register, which is assumed to contain integer data (packed bytes, words, double-words, or quadwords). The destination operand is a 128-bit, 256-bit or 512-bit memory location. The memory operand must be aligned on a 16-byte (128-bit version), 32-byte (VEX.256 encoded version) or 64-byte (512-bit version) boundary otherwise a general-protection exception (#GP) will be generated. The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see “Caching of Temporal vs. Non-Temporal Data” in Chapter 10 in the IA-32 Intel Architecture Software Developer’s Manual, Volume 1.Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with the SFENCE or MFENCE instruction should be used in conjunction with VMOVNTDQ instructions if multiple proces-sors might use different memory types to read/write the destination memory locations.Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, VEX.L must be 0; otherwise instructions will #UD.OperationVMOVNTDQ(EVEX encoded versions) VL = 128, 256, 512DEST[VL-1:0] := SRC[VL-1:0]DEST[MAXVL-1:VL] := 0Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F E7 /rMOVNTDQ m128, xmm1AV/VSSE2Move packed integer values in xmm1 to m128 using non-temporal hint.VEX.128.66.0F.WIG E7 /rVMOVNTDQ m128, xmm1AV/VAVXMove packed integer values in xmm1 to m128 using non-temporal hint.VEX.256.66.0F.WIG E7 /rVMOVNTDQ m256, ymm1AV/VAVXMove packed integer values in ymm1 to m256 using non-temporal hint.EVEX.128.66.0F.W0 E7 /rVMOVNTDQ m128, xmm1BV/VAVX512VLAVX512FMove packed integer values in xmm1 to m128 using non-temporal hint.EVEX.256.66.0F.W0 E7 /rVMOVNTDQ m256, ymm1BV/VAVX512VLAVX512FMove packed integer values in zmm1 to m256 using non-temporal hint.EVEX.512.66.0F.W0 E7 /rVMOVNTDQ m512, zmm1BV/VAVX512FMove packed integer values in zmm1 to m512 using non-temporal hint.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:r/m (w)ModRM:reg (r)NANABFull MemModRM:r/m (w)ModRM:reg (r)NANA1.ModRM.MOD != 011B

image/svg+xmlMOVNTDQ (Legacy and VEX versions)DEST := SRCIntel C/C++ Compiler Intrinsic EquivalentVMOVNTDQ void _mm512_stream_si512(void * p, __m512i a);VMOVNTDQ void _mm256_stream_si256 (__m256i * p, __m256i a);MOVNTDQ void _mm_stream_si128 (__m128i * p, __m128i a);SIMD Floating-Point ExceptionsNoneOther ExceptionsNon-EVEX-encoded instruction, see Exceptions Type1.SSE2 in Table2-18, “Type 1 Class Exception Conditions”. EVEX-encoded instruction, see Table2-45, “Type E1NF Class Exception Conditions”.Additionally:#UDIf VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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