image/svg+xmlMOVLPD—Move Low Packed Double-Precision Floating-Point ValueInstruction Operand EncodingDescriptionThis instruction cannot be used for register to register or memory to memory moves.128-bit Legacy SSE load:Moves a double-precision floating-point value from the source 64-bit memory operand and stores it in the low 64-bits of the destination XMM register. The upper 64bits of the XMM register are preserved. Bits (MAXVL-1:128) of the corresponding destination register are preserved.VEX.128 & EVEX encoded load:Loads a double-precision floating-point value from the source 64-bit memory operand (third operand), merges it with the upper 64-bits of the first source XMM register (second operand), and stores it in the low 128-bits of the destination XMM register (first operand). Bits (MAXVL-1:128) of the corresponding destination register are zeroed.128-bit store:Stores a double-precision floating-point value from the low 64-bits of the XMM register source (second operand) to the 64-bit memory location (first operand).Note: VMOVLPD (store) (VEX.128.66.0F 13 /r) is legal and has the same behavior as the existing 66 0F 13 store. For VMOVLPD (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.If VMOVLPD is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or EVEX.L’L= 1 will cause an #UD exception.OperationMOVLPD (128-bit Legacy SSE load)DEST[63:0] := SRC[63:0]DEST[MAXVL-1:64] (Unmodified)Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F 12 /rMOVLPD xmm1, m64AV/VSSE2Move double-precision floating-point value from m64 to low quadword of xmm1.VEX.128.66.0F.WIG 12 /rVMOVLPD xmm2, xmm1, m64BV/VAVXMerge double-precision floating-point value from m64 and the high quadword of xmm1.EVEX.128.66.0F.W1 12 /rVMOVLPD xmm2, xmm1, m64DV/VAVX512FMerge double-precision floating-point value from m64 and the high quadword of xmm1.66 0F 13/rMOVLPD m64, xmm1CV/VSSE2Move double-precision floating-point value from low quadword of xmm1 to m64.VEX.128.66.0F.WIG 13/rVMOVLPD m64, xmm1CV/VAVXMove double-precision floating-point value from low quadword of xmm1 to m64.EVEX.128.66.0F.W1 13/rVMOVLPD m64, xmm1EV/VAVX512FMove double-precision floating-point value from low quadword of xmm1 to m64.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:r/m (r)VEX.vvvv (r)ModRM:r/m (r)NACNAModRM:r/m (w)ModRM:reg (r)NANADTuple1 ScalarModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NAETuple1 ScalarModRM:r/m (w)ModRM:reg (r)NANA

image/svg+xmlVMOVLPD (VEX.128 & EVEX encoded load)DEST[63:0] := SRC2[63:0]DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0VMOVLPD (store)DEST[63:0] := SRC[63:0]Intel C/C++ Compiler Intrinsic EquivalentMOVLPD __m128d _mm_loadl_pd ( __m128d a, double *p)MOVLPD void _mm_storel_pd (double *p, __m128d a)SIMD Floating-Point ExceptionsNoneOther ExceptionsNon-EVEX-encoded instruction, see Table2-22, “Type 5 Class Exception Conditions”; additionally:#UDIf VEX.L = 1.EVEX-encoded instruction, see Table2-57, “Type E9NF Class Exception Conditions”.

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