image/svg+xmlMOVLHPS—Move Packed Single-Precision Floating-Point Values Low to HighInstruction Operand Encoding1DescriptionThis instruction cannot be used for memory to register moves.128-bit two-argument form:Moves two packed single-precision floating-point values from the low quadword of the second XMM argument (second operand) to the high quadword of the first XMM register (first argument). The low quadword of the desti-nation operand is left unchanged. Bits (MAXVL-1:128) of the corresponding destination register are unmodified.128-bit three-argument forms:Moves two packed single-precision floating-point values from the low quadword of the third XMM argument (third operand) to the high quadword of the destination (first operand). Copies the low quadword from the second XMM argument (second operand) to the low quadword of the destination (first operand). Bits (MAXVL-1:128) of the corresponding destination register are zeroed.If VMOVLHPS is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or EVEX.L’L= 1 will cause an #UD exception.OperationMOVLHPS (128-bit two-argument form)DEST[63:0] (Unmodified)DEST[127:64] := SRC[63:0]DEST[MAXVL-1:128] (Unmodified)VMOVLHPS (128-bit three-argument form - VEX & EVEX)DEST[63:0] := SRC1[63:0]DEST[127:64] := SRC2[63:0]DEST[MAXVL-1:128] := 0Intel C/C++ Compiler Intrinsic EquivalentMOVLHPS __m128 _mm_movelh_ps(__m128 a, __m128 b)SIMD Floating-Point ExceptionsNoneOpcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F 16 /rMOVLHPS xmm1, xmm2RMV/VSSEMove two packed single-precision floating-point values from low quadword of xmm2 to high quadword of xmm1.VEX.128.0F.WIG 16 /rVMOVLHPS xmm1, xmm2, xmm3RVMV/VAVXMerge two packed single-precision floating-point values from low quadword of xmm3 and low quadword of xmm2.EVEX.128.0F.W0 16 /rVMOVLHPS xmm1, xmm2, xmm3RVMV/VAVX512FMerge two packed single-precision floating-point values from low quadword of xmm3 and low quadword of xmm2.Op/EnOperand 1Operand 2Operand 3Operand 4RMModRM:reg (w)ModRM:r/m (r)NANARVMModRM:reg (w)vvvv (r)ModRM:r/m (r)NA1.ModRM.MOD = 011B required

image/svg+xmlOther ExceptionsNon-EVEX-encoded instruction, see Table2-24, “Type 7 Class Exception Conditions”; additionally:#UDIf VEX.L = 1.EVEX-encoded instruction, see Exceptions Type E7NM.128 in Table2-55, “Type E7NM Class Exception Conditions”.

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