image/svg+xml MOVHLPS—Move Packed Single-Precision Floating-Point Values High to Low Instruction Operand Encoding 1 Description This instruction cannot be used for memory to register moves. 128-bit two-argument form: Moves two packed single-precision floating-point values from the high quadword of the second XMM argument (second operand) to the low quadword of the first XMM register (first argument). The quadword at bits 127:64 of the destination operand is left unchanged. Bits (MAXVL-1:128) of the corresponding destination register remain unchanged. 128-bit and EVEX three-argument form Moves two packed single-precision floating-point values from the high quadword of the third XMM argument (third operand) to the low quadword of the destination (first operand). Copies the high quadword from the second XMM argument (second operand) to the high quadword of the destination (first operand). Bits (MAXVL-1:128) of the corresponding destination register are zeroed. If VMOVHLPS is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or EVEX.L’L= 1 will cause an #UD exception. Operation MOVHLPS (128-bit two-argument form) DEST[63:0] := SRC[127:64] DEST[MAXVL-1:64] (Unmodified) VMOVHLPS (128-bit three-argument form - VEX & EVEX) DEST[63:0] := SRC2[127:64] DEST[127:64] := SRC1[127:64] DEST[MAXVL-1:128] := 0 Intel C/C++ Compiler Intrinsic Equivalent MOVHLPS __m128 _mm_movehl_ps(__m128 a, __m128 b) SIMD Floating-Point Exceptions None Opcode/ Instruction Op / En 64/32 bit Mode Support CPUID Feature Flag Description NP 0F 12 /r MOVHLPS xmm1, xmm2 RMV/VSSEMove two packed single-precision floating-point values from high quadword of xmm2 to low quadword of xmm1. VEX.128.0F.WIG 12 /r VMOVHLPS xmm1, xmm2, xmm3 RVMV/VAVXMerge two packed single-precision floating-point values from high quadword of xmm3 and low quadword of xmm2. EVEX.128.0F.W0 12 /r VMOVHLPS xmm1, xmm2, xmm3 RVMV/VAVX512FMerge two packed single-precision floating-point values from high quadword of xmm3 and low quadword of xmm2. Op/EnOperand 1Operand 2Operand 3Operand 4 RMModRM:reg (w)ModRM:r/m (r)NANA RVMModRM:reg (w)vvvv (r)ModRM:r/m (r)NA 1.ModRM.MOD = 011B required image/svg+xml Other Exceptions Non-EVEX-encoded instruction, see Table2-24, “Type 7 Class Exception Conditions”; additionally: #UDIf VEX.L = 1. EVEX-encoded instruction, see Exceptions Type E7NM.128 in Table2-55, “Type E7NM Class Exception Conditions”. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .