image/svg+xmlMOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer ValuesOpcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionF3 0F 6F /rMOVDQU xmm1, xmm2/m128AV/VSSE2Move unaligned packed integer values from xmm2/m128 to xmm1. F3 0F 7F /rMOVDQU xmm2/m128, xmm1BV/VSSE2Move unaligned packed integer values from xmm1 to xmm2/m128. VEX.128.F3.0F.WIG 6F /rVMOVDQU xmm1, xmm2/m128AV/VAVXMove unaligned packed integer values from xmm2/m128 to xmm1. VEX.128.F3.0F.WIG 7F /rVMOVDQU xmm2/m128, xmm1BV/VAVXMove unaligned packed integer values from xmm1 to xmm2/m128.VEX.256.F3.0F.WIG 6F /rVMOVDQU ymm1, ymm2/m256AV/VAVXMove unaligned packed integer values from ymm2/m256 to ymm1.VEX.256.F3.0F.WIG 7F /rVMOVDQU ymm2/m256, ymm1BV/VAVXMove unaligned packed integer values from ymm1 to ymm2/m256.EVEX.128.F2.0F.W0 6F /rVMOVDQU8 xmm1 {k1}{z}, xmm2/m128CV/VAVX512VLAVX512BWMove unaligned packed byte integer values from xmm2/m128 to xmm1 using writemask k1.EVEX.256.F2.0F.W0 6F /rVMOVDQU8 ymm1 {k1}{z}, ymm2/m256 CV/VAVX512VLAVX512BWMove unaligned packed byte integer values from ymm2/m256 to ymm1 using writemask k1.EVEX.512.F2.0F.W0 6F /rVMOVDQU8 zmm1 {k1}{z}, zmm2/m512CV/VAVX512BWMove unaligned packed byte integer values from zmm2/m512 to zmm1 using writemask k1.EVEX.128.F2.0F.W0 7F /rVMOVDQU8 xmm2/m128 {k1}{z}, xmm1DV/VAVX512VLAVX512BWMove unaligned packed byte integer values from xmm1 to xmm2/m128 using writemask k1.EVEX.256.F2.0F.W0 7F /rVMOVDQU8 ymm2/m256 {k1}{z}, ymm1DV/VAVX512VLAVX512BWMove unaligned packed byte integer values from ymm1 to ymm2/m256 using writemask k1.EVEX.512.F2.0F.W0 7F /rVMOVDQU8 zmm2/m512 {k1}{z}, zmm1DV/VAVX512BWMove unaligned packed byte integer values from zmm1 to zmm2/m512 using writemask k1.EVEX.128.F2.0F.W1 6F /rVMOVDQU16 xmm1 {k1}{z}, xmm2/m128 CV/VAVX512VLAVX512BWMove unaligned packed word integer values from xmm2/m128 to xmm1 using writemask k1.EVEX.256.F2.0F.W1 6F /rVMOVDQU16 ymm1 {k1}{z}, ymm2/m256CV/VAVX512VLAVX512BWMove unaligned packed word integer values from ymm2/m256 to ymm1 using writemask k1.EVEX.512.F2.0F.W1 6F /rVMOVDQU16 zmm1 {k1}{z}, zmm2/m512 CV/VAVX512BWMove unaligned packed word integer values from zmm2/m512 to zmm1 using writemask k1.EVEX.128.F2.0F.W1 7F /rVMOVDQU16 xmm2/m128 {k1}{z}, xmm1DV/VAVX512VLAVX512BWMove unaligned packed word integer values from xmm1 to xmm2/m128 using writemask k1.EVEX.256.F2.0F.W1 7F /rVMOVDQU16 ymm2/m256 {k1}{z}, ymm1DV/VAVX512VLAVX512BWMove unaligned packed word integer values from ymm1 to ymm2/m256 using writemask k1.EVEX.512.F2.0F.W1 7F /rVMOVDQU16 zmm2/m512 {k1}{z}, zmm1DV/VAVX512BWMove unaligned packed word integer values from zmm1 to zmm2/m512 using writemask k1.EVEX.128.F3.0F.W0 6F /rVMOVDQU32 xmm1 {k1}{z}, xmm2/mm128CV/VAVX512VLAVX512FMove unaligned packed doubleword integer values from xmm2/m128 to xmm1 using writemask k1.

image/svg+xmlInstruction Operand EncodingDescriptionNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.EVEX encoded versions:Moves 128, 256 or 512 bits of packed byte/word/doubleword/quadword integer values from the source operand (the second operand) to the destination operand (first operand). This instruction can be used to load a vector register from a memory location, to store the contents of a vector register into a memory location, or to move data between two vector registers. EVEX.256.F3.0F.W0 6F /rVMOVDQU32 ymm1 {k1}{z}, ymm2/m256 CV/VAVX512VLAVX512FMove unaligned packed doubleword integer values from ymm2/m256 to ymm1 using writemask k1.EVEX.512.F3.0F.W0 6F /rVMOVDQU32 zmm1 {k1}{z}, zmm2/m512CV/VAVX512FMove unaligned packed doubleword integer values from zmm2/m512 to zmm1 using writemask k1.EVEX.128.F3.0F.W0 7F /rVMOVDQU32 xmm2/m128 {k1}{z}, xmm1DV/VAVX512VLAVX512FMove unaligned packed doubleword integer values from xmm1 to xmm2/m128 using writemask k1.EVEX.256.F3.0F.W0 7F /rVMOVDQU32 ymm2/m256 {k1}{z}, ymm1DV/VAVX512VLAVX512FMove unaligned packed doubleword integer values from ymm1 to ymm2/m256 using writemask k1.EVEX.512.F3.0F.W0 7F /rVMOVDQU32 zmm2/m512 {k1}{z}, zmm1DV/VAVX512FMove unaligned packed doubleword integer values from zmm1 to zmm2/m512 using writemask k1.EVEX.128.F3.0F.W1 6F /rVMOVDQU64 xmm1 {k1}{z}, xmm2/m128 CV/VAVX512VLAVX512FMove unaligned packed quadword integer values from xmm2/m128 to xmm1 using writemask k1.EVEX.256.F3.0F.W1 6F /rVMOVDQU64 ymm1 {k1}{z}, ymm2/m256CV/VAVX512VLAVX512FMove unaligned packed quadword integer values from ymm2/m256 to ymm1 using writemask k1.EVEX.512.F3.0F.W1 6F /rVMOVDQU64 zmm1 {k1}{z}, zmm2/m512CV/VAVX512FMove unaligned packed quadword integer values from zmm2/m512 to zmm1 using writemask k1.EVEX.128.F3.0F.W1 7F /rVMOVDQU64 xmm2/m128 {k1}{z}, xmm1DV/VAVX512VLAVX512FMove unaligned packed quadword integer values from xmm1 to xmm2/m128 using writemask k1.EVEX.256.F3.0F.W1 7F /rVMOVDQU64 ymm2/m256 {k1}{z}, ymm1DV/VAVX512VLAVX512FMove unaligned packed quadword integer values from ymm1 to ymm2/m256 using writemask k1.EVEX.512.F3.0F.W1 7F /rVMOVDQU64 zmm2/m512 {k1}{z}, zmm1DV/VAVX512FMove unaligned packed quadword integer values from zmm1 to zmm2/m512 using writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)NANABNAModRM:r/m (w)ModRM:reg (r)NANACFull MemModRM:reg (w)ModRM:r/m (r)NANADFull MemModRM:r/m (w)ModRM:reg (r)NANAOpcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription

image/svg+xmlThe destination operand is updated at 8-bit (VMOVDQU8), 16-bit (VMOVDQU16), 32-bit (VMOVDQU32), or 64-bit (VMOVDQU64) granularity according to the writemask.VEX.256 encoded version:Moves 256 bits of packed integer values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM registers. Bits (MAXVL-1:256) of the destination register are zeroed.128-bit versions:Moves 128 bits of packed integer values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers. 128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding destination register remain unchanged.When the source or destination operand is a memory operand, the operand may be unaligned to any alignment without causing a general-protection exception (#GP) to be generatedVEX.128 encoded version: Bits (MAXVL-1:128) of the destination register are zeroed.OperationVMOVDQU8 (EVEX encoded versions, register-copy form)(KL, VL) = (16, 128), (32, 256), (64, 512)FOR j := 0 TO KL-1i := j * 8IF k1[j] OR *no writemask*THEN DEST[i+7:i] := SRC[i+7:i]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+7:i] remains unchanged*ELSE DEST[i+7:i] := 0 ; zeroing-maskingFIFI;ENDFORDEST[MAXVL-1:VL] := 0VMOVDQU8 (EVEX encoded versions, store-form) (KL, VL) = (16, 128), (32, 256), (64, 512)FOR j := 0 TO KL-1i := j * 8IF k1[j] OR *no writemask*THEN DEST[i+7:i] := SRC[i+7:i]ELSE *DEST[i+7:i] remains unchanged*; merging-maskingFI;ENDFOR;

image/svg+xmlVMOVDQU8 (EVEX encoded versions, load-form) (KL, VL) = (16, 128), (32, 256), (64, 512)FOR j := 0 TO KL-1i := j * 8IF k1[j] OR *no writemask*THEN DEST[i+7:i] := SRC[i+7:i]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+7:i] remains unchanged*ELSE DEST[i+7:i] := 0 ; zeroing-maskingFIFI;ENDFORDEST[MAXVL-1:VL] := 0VMOVDQU16 (EVEX encoded versions, register-copy form)(KL, VL) = (8, 128), (16, 256), (32, 512)FOR j := 0 TO KL-1i := j * 16IF k1[j] OR *no writemask*THEN DEST[i+15:i] := SRC[i+15:i]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+15:i] remains unchanged*ELSE DEST[i+15:i] := 0 ; zeroing-maskingFIFI;ENDFORDEST[MAXVL-1:VL] := 0VMOVDQU16 (EVEX encoded versions, store-form) (KL, VL) = (8, 128), (16, 256), (32, 512)FOR j := 0 TO KL-1i := j * 16IF k1[j] OR *no writemask*THEN DEST[i+15:i] := SRC[i+15:i]ELSE *DEST[i+15:i] remains unchanged*; merging-maskingFI;ENDFOR;

image/svg+xmlVMOVDQU16 (EVEX encoded versions, load-form) (KL, VL) = (8, 128), (16, 256), (32, 512)FOR j := 0 TO KL-1i := j * 16IF k1[j] OR *no writemask*THEN DEST[i+15:i] := SRC[i+15:i]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+15:i] remains unchanged*ELSE DEST[i+15:i] := 0 ; zeroing-maskingFIFI;ENDFORDEST[MAXVL-1:VL] := 0VMOVDQU32 (EVEX encoded versions, register-copy form)(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no writemask*THEN DEST[i+31:i] := SRC[i+31:i]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE DEST[i+31:i] := 0 ; zeroing-maskingFIFI;ENDFORDEST[MAXVL-1:VL] := 0VMOVDQU32 (EVEX encoded versions, store-form) (KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no writemask*THEN DEST[i+31:i] := SRC[i+31:i]ELSE *DEST[i+31:i] remains unchanged*; merging-maskingFI;ENDFOR;

image/svg+xmlVMOVDQU32 (EVEX encoded versions, load-form) (KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no writemask*THEN DEST[i+31:i] := SRC[i+31:i]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE DEST[i+31:i] := 0 ; zeroing-maskingFIFI;ENDFORDEST[MAXVL-1:VL] := 0VMOVDQU64 (EVEX encoded versions, register-copy form)(KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64IF k1[j] OR *no writemask*THEN DEST[i+63:i] := SRC[i+63:i]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+63:i] remains unchanged*ELSE DEST[i+63:i] := 0 ; zeroing-maskingFIFI;ENDFORDEST[MAXVL-1:VL] := 0VMOVDQU64 (EVEX encoded versions, store-form) (KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64IF k1[j] OR *no writemask*THEN DEST[i+63:i] := SRC[i+63:i]ELSE *DEST[i+63:i] remains unchanged*; merging-maskingFI;ENDFOR;

image/svg+xmlVMOVDQU64 (EVEX encoded versions, load-form) (KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64IF k1[j] OR *no writemask*THEN DEST[i+63:i] := SRC[i+63:i]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+63:i] remains unchanged*ELSE DEST[i+63:i] := 0 ; zeroing-maskingFIFI;ENDFORDEST[MAXVL-1:VL] := 0VMOVDQU (VEX.256 encoded version, load - and register copy)DEST[255:0] := SRC[255:0]DEST[MAXVL-1:256] := 0VMOVDQU (VEX.256 encoded version, store-form)DEST[255:0] := SRC[255:0]VMOVDQU (VEX.128 encoded version)DEST[127:0] := SRC[127:0]DEST[MAXVL-1:128] := 0VMOVDQU (128-bit load- and register-copy- form Legacy SSE version)DEST[127:0] := SRC[127:0]DEST[MAXVL-1:128] (Unmodified)(V)MOVDQU (128-bit store-form version)DEST[127:0] := SRC[127:0]Intel C/C++ Compiler Intrinsic EquivalentVMOVDQU16 __m512i _mm512_mask_loadu_epi16(__m512i s, __mmask32 k, void * sa); VMOVDQU16 __m512i _mm512_maskz_loadu_epi16( __mmask32 k, void * sa); VMOVDQU16 void _mm512_mask_storeu_epi16(void * d, __mmask32 k, __m512i a); VMOVDQU16 __m256i _mm256_mask_loadu_epi16(__m256i s, __mmask16 k, void * sa); VMOVDQU16 __m256i _mm256_maskz_loadu_epi16( __mmask16 k, void * sa); VMOVDQU16 void _mm256_mask_storeu_epi16(void * d, __mmask16 k, __m256i a); VMOVDQU16 __m128i _mm_mask_loadu_epi16(__m128i s, __mmask8 k, void * sa); VMOVDQU16 __m128i _mm_maskz_loadu_epi16( __mmask8 k, void * sa); VMOVDQU16 void _mm_mask_storeu_epi16(void * d, __mmask8 k, __m128i a); VMOVDQU32 __m512i _mm512_loadu_epi32( void * sa); VMOVDQU32 __m512i _mm512_mask_loadu_epi32(__m512i s, __mmask16 k, void * sa); VMOVDQU32 __m512i _mm512_maskz_loadu_epi32( __mmask16 k, void * sa); VMOVDQU32 void _mm512_storeu_epi32(void * d, __m512i a); VMOVDQU32 void _mm512_mask_storeu_epi32(void * d, __mmask16 k, __m512i a); VMOVDQU32 __m256i _mm256_mask_loadu_epi32(__m256i s, __mmask8 k, void * sa); VMOVDQU32 __m256i _mm256_maskz_loadu_epi32( __mmask8 k, void * sa); VMOVDQU32 void _mm256_storeu_epi32(void * d, __m256i a); VMOVDQU32 void _mm256_mask_storeu_epi32(void * d, __mmask8 k, __m256i a); VMOVDQU32 __m128i _mm_mask_loadu_epi32(__m128i s, __mmask8 k, void * sa); VMOVDQU32 __m128i _mm_maskz_loadu_epi32( __mmask8 k, void * sa);

image/svg+xmlVMOVDQU32 void _mm_storeu_epi32(void * d, __m128i a); VMOVDQU32 void _mm_mask_storeu_epi32(void * d, __mmask8 k, __m128i a); VMOVDQU64 __m512i _mm512_loadu_epi64( void * sa); VMOVDQU64 __m512i _mm512_mask_loadu_epi64(__m512i s, __mmask8 k, void * sa); VMOVDQU64 __m512i _mm512_maskz_loadu_epi64( __mmask8 k, void * sa); VMOVDQU64 void _mm512_storeu_epi64(void * d, __m512i a); VMOVDQU64 void _mm512_mask_storeu_epi64(void * d, __mmask8 k, __m512i a); VMOVDQU64 __m256i _mm256_mask_loadu_epi64(__m256i s, __mmask8 k, void * sa); VMOVDQU64 __m256i _mm256_maskz_loadu_epi64( __mmask8 k, void * sa); VMOVDQU64 void _mm256_storeu_epi64(void * d, __m256i a); VMOVDQU64 void _mm256_mask_storeu_epi64(void * d, __mmask8 k, __m256i a); VMOVDQU64 __m128i _mm_mask_loadu_epi64(__m128i s, __mmask8 k, void * sa); VMOVDQU64 __m128i _mm_maskz_loadu_epi64( __mmask8 k, void * sa); VMOVDQU64 void _mm_storeu_epi64(void * d, __m128i a); VMOVDQU64 void _mm_mask_storeu_epi64(void * d, __mmask8 k, __m128i a); VMOVDQU8 __m512i _mm512_mask_loadu_epi8(__m512i s, __mmask64 k, void * sa); VMOVDQU8 __m512i _mm512_maskz_loadu_epi8( __mmask64 k, void * sa); VMOVDQU8 void _mm512_mask_storeu_epi8(void * d, __mmask64 k, __m512i a); VMOVDQU8 __m256i _mm256_mask_loadu_epi8(__m256i s, __mmask32 k, void * sa); VMOVDQU8 __m256i _mm256_maskz_loadu_epi8( __mmask32 k, void * sa); VMOVDQU8 void _mm256_mask_storeu_epi8(void * d, __mmask32 k, __m256i a); VMOVDQU8 __m128i _mm_mask_loadu_epi8(__m128i s, __mmask16 k, void * sa); VMOVDQU8 __m128i _mm_maskz_loadu_epi8( __mmask16 k, void * sa); VMOVDQU8 void _mm_mask_storeu_epi8(void * d, __mmask16 k, __m128i a); MOVDQU __m256i _mm256_loadu_si256 (__m256i * p);MOVDQU _mm256_storeu_si256(_m256i *p, __m256i a);MOVDQU __m128i _mm_loadu_si128 (__m128i * p);MOVDQU _mm_storeu_si128(__m128i *p, __m128i a);SIMD Floating-Point ExceptionsNoneOther ExceptionsNon-EVEX-encoded instruction, see Table2-21, “Type 4 Class Exception Conditions”.EVEX-encoded instruction, see Exceptions Type E4.nb in Table2-49, “Type E4 Class Exception Conditions”.Additionally:#UDIf EVEX.vvvv != 1111B or VEX.vvvv != 1111B.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.